DE69023253D1 - Steuergerät für DRAM. - Google Patents

Steuergerät für DRAM.

Info

Publication number
DE69023253D1
DE69023253D1 DE69023253T DE69023253T DE69023253D1 DE 69023253 D1 DE69023253 D1 DE 69023253D1 DE 69023253 T DE69023253 T DE 69023253T DE 69023253 T DE69023253 T DE 69023253T DE 69023253 D1 DE69023253 D1 DE 69023253D1
Authority
DE
Germany
Prior art keywords
dram
control unit
unit
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69023253T
Other languages
English (en)
Other versions
DE69023253T2 (de
Inventor
Toshiyasu Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba TEC Corp
Original Assignee
Tokyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electric Co Ltd filed Critical Tokyo Electric Co Ltd
Publication of DE69023253D1 publication Critical patent/DE69023253D1/de
Application granted granted Critical
Publication of DE69023253T2 publication Critical patent/DE69023253T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
DE69023253T 1989-02-10 1990-02-08 Steuergerät für DRAM. Expired - Fee Related DE69023253T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1032263A JPH02210685A (ja) 1989-02-10 1989-02-10 Ｄｒａｍコントローラ

Publications (2)

Publication Number Publication Date
DE69023253D1 true DE69023253D1 (de) 1995-12-07
DE69023253T2 DE69023253T2 (de) 1996-06-27

Family

ID=12354127

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69023253T Expired - Fee Related DE69023253T2 (de) 1989-02-10 1990-02-08 Steuergerät für DRAM.

Country Status (6)

Country Link
US (1) US5153856A (de)
EP (1) EP0383195B1 (de)
JP (1) JPH02210685A (de)
KR (1) KR920005283B1 (de)
AU (1) AU604617B2 (de)
DE (1) DE69023253T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
JP3225531B2 (ja) * 1990-05-15 2001-11-05 セイコーエプソン株式会社 メモリカード
JPH04114395A (ja) * 1990-09-05 1992-04-15 Nec Corp 半導体記憶回路
TW247359B (en) * 1993-08-30 1995-05-11 Hitachi Seisakusyo Kk Liquid crystal display and liquid crystal driver
JPH09161471A (ja) * 1995-12-06 1997-06-20 Internatl Business Mach Corp <Ibm> Ｄｒａｍシステム、ｄｒａｍシステムの動作方法
SE512773C2 (sv) 1998-10-28 2000-05-08 Imsys Ab Metod och anordning för kontroll/access av DRAM-minnen
US6603705B2 (en) 2000-10-06 2003-08-05 Pmc-Sierra Ltd. Method of allowing random access to rambus DRAM for short burst of data
US9753858B2 (en) * 2011-11-30 2017-09-05 Advanced Micro Devices, Inc. DRAM cache with tags and data jointly stored in physical rows

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5971194A (ja) * 1982-10-16 1984-04-21 Olympus Optical Co Ltd ダイナミツクメモリの制御方式
US4513372A (en) * 1982-11-15 1985-04-23 Data General Corporation Universal memory
JPS6079593A (ja) * 1983-10-07 1985-05-07 Hitachi Ltd 半導体集積回路システム
JPS61162886A (ja) * 1985-01-11 1986-07-23 Casio Comput Co Ltd メモリアクセス方式
JPS63144491A (ja) * 1986-12-05 1988-06-16 Alps Electric Co Ltd ダイナミツクｒａｍのコントロ−ル方式
JP2515772B2 (ja) * 1986-12-26 1996-07-10 株式会社日立製作所 情報処理装置

Also Published As

Publication number Publication date
AU4920790A (en) 1990-08-23
KR920005283B1 (ko) 1992-06-29
EP0383195B1 (de) 1995-11-02
JPH02210685A (ja) 1990-08-22
AU604617B2 (en) 1990-12-20
EP0383195A2 (de) 1990-08-22
EP0383195A3 (de) 1992-03-04
KR900013396A (ko) 1990-09-05
US5153856A (en) 1992-10-06
DE69023253T2 (de) 1996-06-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee