DE69023679T2 - Gerät, das fähig ist, die Anzahl von Wartezuständen für den Zugriff zu variieren. - Google Patents

Gerät, das fähig ist, die Anzahl von Wartezuständen für den Zugriff zu variieren.

Info

Publication number
DE69023679T2
DE69023679T2 DE69023679T DE69023679T DE69023679T2 DE 69023679 T2 DE69023679 T2 DE 69023679T2 DE 69023679 T DE69023679 T DE 69023679T DE 69023679 T DE69023679 T DE 69023679T DE 69023679 T2 DE69023679 T2 DE 69023679T2
Authority
DE
Germany
Prior art keywords
vary
access
waiting states
waiting
states
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69023679T
Other languages
English (en)
Other versions
DE69023679D1 (de
Inventor
Akihiro Shimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Application granted granted Critical
Publication of DE69023679D1 publication Critical patent/DE69023679D1/de
Publication of DE69023679T2 publication Critical patent/DE69023679T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
DE69023679T 1989-03-08 1990-02-28 Gerät, das fähig ist, die Anzahl von Wartezuständen für den Zugriff zu variieren. Expired - Fee Related DE69023679T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1057303A JPH02235156A (ja) 1989-03-08 1989-03-08 情報処理装置

Publications (2)

Publication Number Publication Date
DE69023679D1 DE69023679D1 (de) 1996-01-04
DE69023679T2 true DE69023679T2 (de) 1996-05-02

Family

ID=13051791

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69023679T Expired - Fee Related DE69023679T2 (de) 1989-03-08 1990-02-28 Gerät, das fähig ist, die Anzahl von Wartezuständen für den Zugriff zu variieren.

Country Status (5)

Country Link
US (1) US5809517A (de)
EP (1) EP0386935B1 (de)
JP (1) JPH02235156A (de)
DE (1) DE69023679T2 (de)
SG (1) SG43275A1 (de)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03210649A (ja) * 1990-01-12 1991-09-13 Fujitsu Ltd マイクロコンピュータおよびそのバスサイクル制御方法
GB2244174B (en) * 1990-05-15 1994-10-05 Intel Corp Apparatus for selecting number of wait states in burst eprom architecture
US5522064A (en) * 1990-10-01 1996-05-28 International Business Machines Corporation Data processing apparatus for dynamically setting timings in a dynamic memory system
JPH04192047A (ja) * 1990-11-27 1992-07-10 Toshiba Corp パーソナルコンピュータ
JPH0715665B2 (ja) * 1991-06-10 1995-02-22 インターナショナル・ビジネス・マシーンズ・コーポレイション パーソナルコンピユータ
US5481675A (en) * 1992-05-12 1996-01-02 International Business Machines Corporation Asynchronous serial communication system for delaying with software dwell time a receiving computer's acknowledgement in order for the transmitting computer to see the acknowledgement
US6067606A (en) * 1997-12-15 2000-05-23 Intel Corporation Computer processor with dynamic setting of latency values for memory access
US6356987B1 (en) * 1999-03-10 2002-03-12 Atmel Corporation Microprocessing device having programmable wait states
US6407949B1 (en) * 1999-12-17 2002-06-18 Qualcomm, Incorporated Mobile communication device having integrated embedded flash and SRAM memory
US6714993B1 (en) 2000-05-22 2004-03-30 Legerity, Inc. Programmable memory based control for generating optimal timing to access serial flash devices
JP2002091905A (ja) * 2000-09-20 2002-03-29 Mitsubishi Electric Corp 半導体装置およびアクセスウェイト数変更プログラムを記録したコンピュータ読み取り可能な記録媒体
US6662285B1 (en) * 2001-01-09 2003-12-09 Xilinx, Inc. User configurable memory system having local and global memory blocks
ITTO20010333A1 (it) * 2001-04-06 2002-10-06 St Microelectronics Srl Dispositivo e metodo di gestione dei cicli di attesa durante la lettura di una memoria non volatile.
US6605962B2 (en) 2001-05-06 2003-08-12 Altera Corporation PLD architecture for flexible placement of IP function blocks
US7076595B1 (en) 2001-05-18 2006-07-11 Xilinx, Inc. Programmable logic device including programmable interface core and central processing unit
US7420392B2 (en) * 2001-09-28 2008-09-02 Xilinx, Inc. Programmable gate array and embedded circuitry initialization and processing
US6798239B2 (en) * 2001-09-28 2004-09-28 Xilinx, Inc. Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
US6983405B1 (en) 2001-11-16 2006-01-03 Xilinx, Inc., Method and apparatus for testing circuitry embedded within a field programmable gate array
US6996758B1 (en) 2001-11-16 2006-02-07 Xilinx, Inc. Apparatus for testing an interconnecting logic fabric
US6886092B1 (en) 2001-11-19 2005-04-26 Xilinx, Inc. Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion
US6820248B1 (en) 2002-02-14 2004-11-16 Xilinx, Inc. Method and apparatus for routing interconnects to devices with dissimilar pitches
US6976160B1 (en) 2002-02-22 2005-12-13 Xilinx, Inc. Method and system for controlling default values of flip-flops in PGA/ASIC-based designs
US6754882B1 (en) 2002-02-22 2004-06-22 Xilinx, Inc. Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC)
US7007121B1 (en) 2002-02-27 2006-02-28 Xilinx, Inc. Method and apparatus for synchronized buses
US6934922B1 (en) 2002-02-27 2005-08-23 Xilinx, Inc. Timing performance analysis
US7111217B1 (en) 2002-02-28 2006-09-19 Xilinx, Inc. Method and system for flexibly nesting JTAG TAP controllers for FPGA-based system-on-chip (SoC)
US6839874B1 (en) 2002-02-28 2005-01-04 Xilinx, Inc. Method and apparatus for testing an embedded device
US7111220B1 (en) 2002-03-01 2006-09-19 Xilinx, Inc. Network physical layer with embedded multi-standard CRC generator
US7088767B1 (en) 2002-03-01 2006-08-08 Xilinx, Inc. Method and apparatus for operating a transceiver in different data rates
US7187709B1 (en) 2002-03-01 2007-03-06 Xilinx, Inc. High speed configurable transceiver architecture
US6961919B1 (en) 2002-03-04 2005-11-01 Xilinx, Inc. Method of designing integrated circuit having both configurable and fixed logic circuitry
US6973405B1 (en) 2002-05-22 2005-12-06 Xilinx, Inc. Programmable interactive verification agent
US6941433B1 (en) * 2002-05-22 2005-09-06 Juniper Networks, Inc. Systems and methods for memory read response latency detection
US6772405B1 (en) 2002-06-13 2004-08-03 Xilinx, Inc. Insertable block tile for interconnecting to a device embedded in an integrated circuit
US7085973B1 (en) 2002-07-09 2006-08-01 Xilinx, Inc. Testing address lines of a memory controller
US7099426B1 (en) 2002-09-03 2006-08-29 Xilinx, Inc. Flexible channel bonding and clock correction operations on a multi-block data path
US7092865B1 (en) 2002-09-10 2006-08-15 Xilinx, Inc. Method and apparatus for timing modeling
US7278057B2 (en) * 2003-07-31 2007-10-02 International Business Machines Corporation Automated hang detection in Java thread dumps
US7421014B2 (en) * 2003-09-11 2008-09-02 Xilinx, Inc. Channel bonding of a plurality of multi-gigabit transceivers
US7846008B2 (en) * 2004-11-29 2010-12-07 Semiquest Inc. Method and apparatus for improved chemical mechanical planarization and CMP pad
US8156297B2 (en) * 2008-04-15 2012-04-10 Microsoft Corporation Smart device recordation

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4954951A (en) * 1970-12-28 1990-09-04 Hyatt Gilbert P System and method for increasing memory performance
GB1561961A (en) * 1977-04-20 1980-03-05 Int Computers Ltd Data processing units
US4608689A (en) * 1981-12-04 1986-08-26 Canon Kabushiki Kaisha Data processing and transfer apparatus
US4636939A (en) * 1982-07-16 1987-01-13 At&T Bell Laboratories Parallel bus protocol
DE3501569C2 (de) * 1984-01-20 1996-07-18 Canon Kk Datenverarbeitungseinrichtung
US4680701A (en) * 1984-04-11 1987-07-14 Texas Instruments Incorporated Asynchronous high speed processor having high speed memories with domino circuits contained therein
US4665495A (en) * 1984-07-23 1987-05-12 Texas Instruments Incorporated Single chip dram controller and CRT controller
US4691289A (en) * 1984-07-23 1987-09-01 Texas Instruments Incorporated State machine standard cell that supports both a Moore and a Mealy implementation
JPS61118850A (ja) * 1984-11-15 1986-06-06 Nec Corp マイクロプロセツサ
JPS61224051A (ja) * 1985-03-29 1986-10-04 Fujitsu Ltd バッファメモリ制御方法
JPS6278640A (ja) * 1985-10-02 1987-04-10 Mitsubishi Electric Corp 主記憶制御装置
IT1215539B (it) * 1987-06-03 1990-02-14 Honeywell Inf Systems Memoria tampone trasparente.
US5038282A (en) * 1988-05-11 1991-08-06 Massachusetts Institute Of Technology Synchronous processor with simultaneous instruction processing and data transfer
US5113518A (en) * 1988-06-03 1992-05-12 Durst Jr Robert T Method and system for preventing unauthorized use of software
US5278974A (en) * 1989-12-04 1994-01-11 Digital Equipment Corporation Method and apparatus for the dynamic adjustment of data transfer timing to equalize the bandwidths of two buses in a computer system having different bandwidths

Also Published As

Publication number Publication date
EP0386935A3 (de) 1991-06-19
EP0386935B1 (de) 1995-11-22
DE69023679D1 (de) 1996-01-04
SG43275A1 (en) 1997-10-17
JPH02235156A (ja) 1990-09-18
US5809517A (en) 1998-09-15
EP0386935A2 (de) 1990-09-12

Similar Documents

Publication Publication Date Title
DE69023679D1 (de) Gerät, das fähig ist, die Anzahl von Wartezuständen für den Zugriff zu variieren.
DE3764980D1 (de) System zum applizieren von medikamenten durch die haut.
NO884170D0 (no) Katalytisk omdanningsprosess.
NL193661B (nl) Koolwaterstofomzettingswerkwijze en -katalysatoren.
DE3751020T2 (de) Einrichtung für die Unterdrückung von Oberwellen.
DE3751530T2 (de) Greifvorrichtung.
DE3779150D1 (de) Multiprozessorsystem.
NO873165D0 (no) Anordning ved hengsel.
DK151187A (da) Metalkomplekskatalysatorer
DE3750938D1 (de) Multiprozessorsystem.
DE3677051D1 (de) Verarbeitungsschaltung, die es erlaubt den akkumulationsdurchsatz zu erhoehen.
DE3876155T3 (de) Dehydrierungskatalysator.
DE3784586D1 (de) Methode, um die desaktivierung von entstickungskatalysatoren zu verhindern.
DE3684293D1 (de) Vielfachprozessorsystem.
DE3779592D1 (de) Alkylierungskatalysatoren und -verfahren.
DE68911917T2 (de) Extraktionsgerät für die Geburtshilfe.
DE3877161T2 (de) Hydrierungs-katalysator.
DE69008945T3 (de) Gerät für die Anwendung von Supraleitfähigkeit.
DE3864431D1 (de) Reaktor.
DE3885543D1 (de) Dehydrierungskatalysator.
FI873865A (fi) Katalytisk konverter.
NO884172D0 (no) Katalytisk omdanningsprosess.
DE3861513D1 (de) Entfernung von katalysatorresten.
DE3787311T2 (de) Falschzwirnvorrichtung.
DE68916413T2 (de) Vermittlungssystem für den gleichzeitigen Datentransfer zwischen Datenprozessoren.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee