DE69115983T2 - Schaltungen und Verfahren zur selektiven Umschaltung negativer Spannungen in integrierten CMOS-Schaltungen - Google Patents

Schaltungen und Verfahren zur selektiven Umschaltung negativer Spannungen in integrierten CMOS-Schaltungen

Info

Publication number
DE69115983T2
DE69115983T2 DE69115983T DE69115983T DE69115983T2 DE 69115983 T2 DE69115983 T2 DE 69115983T2 DE 69115983 T DE69115983 T DE 69115983T DE 69115983 T DE69115983 T DE 69115983T DE 69115983 T2 DE69115983 T2 DE 69115983T2
Authority
DE
Germany
Prior art keywords
circuits
methods
negative voltages
selective switching
integrated cmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69115983T
Other languages
English (en)
Other versions
DE69115983D1 (de
Inventor
Giuliano Imondi
Giulio Marotta
Giulio Porrovecchio
Giuseppe Savarese
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69115983D1 publication Critical patent/DE69115983D1/de
Application granted granted Critical
Publication of DE69115983T2 publication Critical patent/DE69115983T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
DE69115983T 1990-05-08 1991-05-07 Schaltungen und Verfahren zur selektiven Umschaltung negativer Spannungen in integrierten CMOS-Schaltungen Expired - Fee Related DE69115983T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT47927A IT1239781B (it) 1990-05-08 1990-05-08 Circuito e metodo per commutare selettivamente tensioni negative in circuiti integrati cmos

Publications (2)

Publication Number Publication Date
DE69115983D1 DE69115983D1 (de) 1996-02-15
DE69115983T2 true DE69115983T2 (de) 1996-06-27

Family

ID=11263411

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69115983T Expired - Fee Related DE69115983T2 (de) 1990-05-08 1991-05-07 Schaltungen und Verfahren zur selektiven Umschaltung negativer Spannungen in integrierten CMOS-Schaltungen

Country Status (5)

Country Link
US (1) US5319604A (de)
EP (1) EP0456623B1 (de)
JP (1) JP3155290B2 (de)
DE (1) DE69115983T2 (de)
IT (1) IT1239781B (de)

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US20030089929A1 (en) * 2001-02-14 2003-05-15 Rhodes Howard E. Trench photosensor for a CMOS imager
US6232626B1 (en) 1999-02-01 2001-05-15 Micron Technology, Inc. Trench photosensor for a CMOS imager
US6376868B1 (en) 1999-06-15 2002-04-23 Micron Technology, Inc. Multi-layered gate for a CMOS imager
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US6804502B2 (en) 2001-10-10 2004-10-12 Peregrine Semiconductor Corporation Switch circuit and method of switching radio frequency signals
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US7709777B2 (en) * 2003-06-16 2010-05-04 Micron Technology, Inc. Pumps for CMOS imagers
US7910993B2 (en) 2005-07-11 2011-03-22 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFET's using an accumulated charge sink
US7890891B2 (en) 2005-07-11 2011-02-15 Peregrine Semiconductor Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
US9653601B2 (en) 2005-07-11 2017-05-16 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US8742502B2 (en) 2005-07-11 2014-06-03 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US20080076371A1 (en) 2005-07-11 2008-03-27 Alexander Dribinsky Circuit and method for controlling charge injection in radio frequency switches
USRE48965E1 (en) 2005-07-11 2022-03-08 Psemi Corporation Method and apparatus improving gate oxide reliability by controlling accumulated charge
KR100780768B1 (ko) * 2006-04-12 2007-11-30 주식회사 하이닉스반도체 고전압 펌핑장치
US7859240B1 (en) 2007-05-22 2010-12-28 Cypress Semiconductor Corporation Circuit and method for preventing reverse current flow into a voltage regulator from an output thereof
US7742325B2 (en) * 2007-12-17 2010-06-22 Suvolta, Inc. Swapped-body RAM architecture
US9029956B2 (en) 2011-10-26 2015-05-12 Global Foundries, Inc. SRAM cell with individual electrical device threshold control
US9048136B2 (en) 2011-10-26 2015-06-02 GlobalFoundries, Inc. SRAM cell with individual electrical device threshold control
KR101334843B1 (ko) * 2012-08-07 2013-12-02 주식회사 동부하이텍 전압 출력 회로 및 이를 이용한 네거티브 전압 선택 출력 장치
US9590674B2 (en) 2012-12-14 2017-03-07 Peregrine Semiconductor Corporation Semiconductor devices with switchable ground-body connection
US20150236798A1 (en) 2013-03-14 2015-08-20 Peregrine Semiconductor Corporation Methods for Increasing RF Throughput Via Usage of Tunable Filters
US20160006348A1 (en) * 2014-07-07 2016-01-07 Ememory Technology Inc. Charge pump apparatus
US9831857B2 (en) 2015-03-11 2017-11-28 Peregrine Semiconductor Corporation Power splitter with programmable output phase shift
US10236872B1 (en) 2018-03-28 2019-03-19 Psemi Corporation AC coupling modules for bias ladders
US10505530B2 (en) 2018-03-28 2019-12-10 Psemi Corporation Positive logic switch with selectable DC blocking circuit
US10886911B2 (en) 2018-03-28 2021-01-05 Psemi Corporation Stacked FET switch bias ladders
CN110830017B (zh) * 2018-08-10 2023-10-13 圣邦微电子（北京）股份有限公司 一种无功耗片内实现多端口过负压的模拟开关
US11476849B2 (en) 2020-01-06 2022-10-18 Psemi Corporation High power positive logic switch

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Also Published As

Publication number Publication date
JP3155290B2 (ja) 2001-04-09
DE69115983D1 (de) 1996-02-15
EP0456623A3 (en) 1992-10-21
EP0456623A2 (de) 1991-11-13
EP0456623B1 (de) 1996-01-03
JPH0689589A (ja) 1994-03-29
IT1239781B (it) 1993-11-15
IT9047927A0 (it) 1990-05-08
US5319604A (en) 1994-06-07
IT9047927A1 (it) 1991-11-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee