DE69125672T2 - Prozessüberwachungsschaltung und Methode dazu - Google Patents
Prozessüberwachungsschaltung und Methode dazuInfo
- Publication number
- DE69125672T2 DE69125672T2 DE69125672T DE69125672T DE69125672T2 DE 69125672 T2 DE69125672 T2 DE 69125672T2 DE 69125672 T DE69125672 T DE 69125672T DE 69125672 T DE69125672 T DE 69125672T DE 69125672 T2 DE69125672 T2 DE 69125672T2
- Authority
- DE
- Germany
- Prior art keywords
- monitoring circuit
- process monitoring
- circuit
- monitoring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/577,945 US5068547A (en) | 1990-09-05 | 1990-09-05 | Process monitor circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69125672D1 DE69125672D1 (de) | 1997-05-22 |
DE69125672T2 true DE69125672T2 (de) | 1997-07-24 |
Family
ID=24310785
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69125672T Expired - Fee Related DE69125672T2 (de) | 1990-09-05 | 1991-08-30 | Prozessüberwachungsschaltung und Methode dazu |
Country Status (5)
Country | Link |
---|---|
US (1) | US5068547A (de) |
EP (1) | EP0476871B1 (de) |
JP (1) | JP3137269B2 (de) |
KR (1) | KR100237504B1 (de) |
DE (1) | DE69125672T2 (de) |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5486786A (en) * | 1994-08-09 | 1996-01-23 | Lsi Logic Corporation | Process monitor for CMOS integrated circuits |
US5631596A (en) * | 1994-08-09 | 1997-05-20 | Lsi Logic Corporation | Process monitor for CMOS integrated circuits |
FR2737066B1 (fr) * | 1995-07-20 | 1997-09-19 | Matra Mhs | Dispositif de conversion analogique-numerique |
DE19528733C1 (de) * | 1995-08-04 | 1997-01-02 | Siemens Ag | Integrierte Schaltung |
US6005406A (en) * | 1995-12-07 | 1999-12-21 | International Business Machines Corporation | Test device and method facilitating aggressive circuit design |
US5872449A (en) * | 1996-01-26 | 1999-02-16 | Lsi Logic Corporation | Semiconductor package qualification chip |
US5796265A (en) * | 1996-02-29 | 1998-08-18 | Lsi Logic Corporation | Method for metal delay testing in semiconductor devices |
US5796260A (en) * | 1996-03-12 | 1998-08-18 | Honeywell Inc. | Parametric test circuit |
US5751161A (en) * | 1996-04-04 | 1998-05-12 | Lsi Logic Corporation | Update scheme for impedance controlled I/O buffers |
US5654895A (en) * | 1996-04-04 | 1997-08-05 | Lsi Logic Corporation | Process monitor usig impedance controlled I/O controller |
US5867033A (en) * | 1996-05-24 | 1999-02-02 | Lsi Logic Corporation | Circuit for testing the operation of a semiconductor device |
US6097884A (en) * | 1997-12-08 | 2000-08-01 | Lsi Logic Corporation | Probe points and markers for critical paths and integrated circuits |
US6124143A (en) * | 1998-01-26 | 2000-09-26 | Lsi Logic Corporation | Process monitor circuitry for integrated circuits |
US6061814A (en) * | 1998-04-21 | 2000-05-09 | Lsi Logic Corporation | Test circuitry for determining the defect density of a semiconductor process as a function of individual metal layers |
US6185706B1 (en) | 1998-06-12 | 2001-02-06 | Lsi Logic Corporation | Performance monitoring circuitry for integrated circuits |
US6367042B1 (en) | 1998-12-11 | 2002-04-02 | Lsi Logic Corporation | Testing methodology for embedded memories using built-in self repair and identification circuitry |
US6067262A (en) * | 1998-12-11 | 2000-05-23 | Lsi Logic Corporation | Redundancy analysis for embedded memories with built-in self test and built-in self repair |
US6651202B1 (en) | 1999-01-26 | 2003-11-18 | Lsi Logic Corporation | Built-in self repair circuitry utilizing permanent record of defects |
US6389578B1 (en) * | 1999-05-26 | 2002-05-14 | Hewlett-Packard Company | Method and apparatus for determining the strengths and weaknesses of paths in an integrated circuit |
US6449749B1 (en) * | 1999-11-18 | 2002-09-10 | Pdf Solutions, Inc. | System and method for product yield prediction |
US6978229B1 (en) | 1999-11-18 | 2005-12-20 | Pdf Solutions, Inc. | Efficient method for modeling and simulation of the impact of local and global variation on integrated circuits |
WO2001036992A1 (en) | 1999-11-18 | 2001-05-25 | Pdf Solutions, Inc. | The passive multiplexor test structure for intergrated circuit manufacturing |
US6544807B1 (en) * | 2000-11-03 | 2003-04-08 | Lsi Logic Corporation | Process monitor with statistically selected ring oscillator |
US6850075B1 (en) * | 2000-12-22 | 2005-02-01 | Cypress Semiconductor Corp. | SRAM self-timed write stress test mode |
US7205986B2 (en) * | 2002-12-18 | 2007-04-17 | Semiconductor Energy Laboratory Co., Ltd. | Image display device and testing method of the same |
JP4624109B2 (ja) * | 2003-03-25 | 2011-02-02 | 株式会社半導体エネルギー研究所 | 半導体装置の検査回路 |
US7256055B2 (en) | 2003-08-25 | 2007-08-14 | Tau-Metrix, Inc. | System and apparatus for using test structures inside of a chip during the fabrication of the chip |
US7298656B2 (en) * | 2004-04-30 | 2007-11-20 | Infineon Technologies Ag | Process monitoring by comparing delays proportional to test voltages and reference voltages |
US7239163B1 (en) * | 2004-06-23 | 2007-07-03 | Ridgetop Group, Inc. | Die-level process monitor and method |
US7243329B2 (en) * | 2004-07-02 | 2007-07-10 | Altera Corporation | Application-specific integrated circuit equivalents of programmable logic and associated methods |
US7518602B2 (en) * | 2004-12-06 | 2009-04-14 | Semiconductor Energy Laboratory Co., Ltd. | Test circuit and display device having the same |
US8095907B2 (en) | 2007-10-19 | 2012-01-10 | International Business Machines Corporation | Reliability evaluation and system fail warning methods using on chip parametric monitors |
US20100283051A1 (en) * | 2008-01-11 | 2010-11-11 | Nxp B.V. | Monitor cell and monitor cell placement method |
JP5452983B2 (ja) * | 2009-06-03 | 2014-03-26 | 株式会社メガチップス | プロセスモニタ回路およびプロセス特性の判定方法 |
TWI405991B (zh) | 2010-04-29 | 2013-08-21 | Ind Tech Res Inst | 製程偏移偵測裝置與製程偏移偵測方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4146835A (en) * | 1978-03-08 | 1979-03-27 | Western Electric Co., Inc. | Testing the differential response times of a plurality of circuits |
US4392105A (en) * | 1980-12-17 | 1983-07-05 | International Business Machines Corp. | Test circuit for delay measurements on a LSI chip |
US4550405A (en) * | 1982-12-23 | 1985-10-29 | Fairchild Camera And Instrument Corporation | Deskew circuit for automatic test equipment |
WO1985003817A1 (en) * | 1984-02-15 | 1985-08-29 | American Telephone & Telegraph Company | High speed cmos circuits |
US4737670A (en) * | 1984-11-09 | 1988-04-12 | Lsi Logic Corporation | Delay control circuit |
US4712061A (en) * | 1986-02-24 | 1987-12-08 | Gould Inc. | Small propagation delay measurement for digital logic |
US4970454A (en) * | 1986-12-09 | 1990-11-13 | Texas Instruments Incorporated | Packaged semiconductor device with test circuits for determining fabrication parameters |
-
1990
- 1990-09-05 US US07/577,945 patent/US5068547A/en not_active Expired - Lifetime
-
1991
- 1991-08-30 DE DE69125672T patent/DE69125672T2/de not_active Expired - Fee Related
- 1991-08-30 EP EP91307954A patent/EP0476871B1/de not_active Expired - Lifetime
- 1991-09-05 KR KR1019910015499A patent/KR100237504B1/ko not_active IP Right Cessation
- 1991-09-05 JP JP03254847A patent/JP3137269B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR100237504B1 (ko) | 2000-01-15 |
EP0476871B1 (de) | 1997-04-16 |
US5068547A (en) | 1991-11-26 |
KR920007138A (ko) | 1992-04-28 |
JPH0582612A (ja) | 1993-04-02 |
JP3137269B2 (ja) | 2001-02-19 |
DE69125672D1 (de) | 1997-05-22 |
EP0476871A1 (de) | 1992-03-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |