DE69128397T2 - Taktgeneratorschaltung sowie Anordnung zum Empfangen und Senden von Daten - Google Patents

Taktgeneratorschaltung sowie Anordnung zum Empfangen und Senden von Daten

Info

Publication number
DE69128397T2
DE69128397T2 DE69128397T DE69128397T DE69128397T2 DE 69128397 T2 DE69128397 T2 DE 69128397T2 DE 69128397 T DE69128397 T DE 69128397T DE 69128397 T DE69128397 T DE 69128397T DE 69128397 T2 DE69128397 T2 DE 69128397T2
Authority
DE
Germany
Prior art keywords
arrangement
receiving
clock generator
generator circuit
sending data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69128397T
Other languages
English (en)
Other versions
DE69128397D1 (de
Inventor
Toshiyuki Katayama
Norihiko Sugimoto
Shunji Inada
Seiji Kamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Engineering Co Ltd
Hitachi Ltd
Original Assignee
Hitachi Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Engineering Co Ltd
Application granted granted Critical
Publication of DE69128397D1 publication Critical patent/DE69128397D1/de
Publication of DE69128397T2 publication Critical patent/DE69128397T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
DE69128397T 1990-09-28 1991-09-25 Taktgeneratorschaltung sowie Anordnung zum Empfangen und Senden von Daten Expired - Fee Related DE69128397T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25999890A JP2766941B2 (ja) 1990-09-28 1990-09-28 クロック生成装置とデータ送受信装置及びその方法

Publications (2)

Publication Number Publication Date
DE69128397D1 DE69128397D1 (de) 1998-01-22
DE69128397T2 true DE69128397T2 (de) 1998-07-09

Family

ID=17341877

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69128397T Expired - Fee Related DE69128397T2 (de) 1990-09-28 1991-09-25 Taktgeneratorschaltung sowie Anordnung zum Empfangen und Senden von Daten

Country Status (5)

Country Link
US (1) US5379325A (de)
EP (1) EP0477916B1 (de)
JP (1) JP2766941B2 (de)
KR (1) KR100210497B1 (de)
DE (1) DE69128397T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3514532B2 (ja) * 1994-11-30 2004-03-31 富士通株式会社 クロック信号生成装置
US5537062A (en) * 1995-06-07 1996-07-16 Ast Research, Inc. Glitch-free clock enable circuit
KR100193806B1 (ko) * 1995-10-13 1999-06-15 윤종용 교환시스템의 클럭 발생회로 및 방법
US6031396A (en) * 1998-06-12 2000-02-29 National Semiconductor Corporation Circuit for synchronizing asynchronous inputs using dual edge logic design
DE19844936C2 (de) * 1998-09-30 2001-02-01 Siemens Ag Schaltung zur Erzeugung eines Ausgangssignals in Abhängigkeit von zwei Eingangssignalen
DE19848211B4 (de) * 1998-10-20 2004-02-05 Honeywell Ag Datenübertragungsverfahren
JP2002091604A (ja) 2000-09-19 2002-03-29 Mitsubishi Electric Corp クロック発生回路
US7230884B2 (en) * 2003-01-03 2007-06-12 The Sapling Company, Inc. Clock diagnostics
CN103548001B (zh) * 2010-12-22 2015-11-25 通用电气能源能量变换技术有限公司 隔离模块之间提供数据通信、同步和故障检测的通信架构
US10243545B2 (en) * 2017-02-06 2019-03-26 Stmicroelectronics Asia Pacific Pte Ltd Shift register utilizing latches controlled by dual non-overlapping clocks

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56132043A (en) * 1980-03-19 1981-10-16 Sony Corp Bit clock reproducing circuit
JPS57116459A (en) * 1981-01-13 1982-07-20 Toshiba Corp Clock regenerating circuit
US4521897A (en) * 1983-07-29 1985-06-04 Zenith Electronics Corporation Apparatus for synchronizing the operation of master and slave counters
EP0153107A3 (de) * 1984-02-10 1987-02-04 Prime Computer, Inc. Gerät und Verfahren zur Taktrückgewinnung für ein ringförmiges Datenübertragungsnetzwerk
US4694196A (en) * 1984-12-07 1987-09-15 American Telephone And Telegraph Company And At&T Information Systems Clock recovery circuit
US4926445A (en) * 1987-07-01 1990-05-15 The United States Of America As Represented By The Secretary Of The Air Force External asynchronous input tester for bit slice machines
JP2845438B2 (ja) * 1987-10-19 1999-01-13 株式会社東芝 高速ディジタルｉｃ
US5173618A (en) * 1990-05-14 1992-12-22 Vlsi Technology, Inc. Clock generator for providing a pair of nonoverlapping clock signals with adjustable skew

Also Published As

Publication number Publication date
KR920007387A (ko) 1992-04-28
JP2766941B2 (ja) 1998-06-18
EP0477916A2 (de) 1992-04-01
EP0477916B1 (de) 1997-12-10
JPH04137935A (ja) 1992-05-12
EP0477916A3 (en) 1993-06-30
US5379325A (en) 1995-01-03
DE69128397D1 (de) 1998-01-22
KR100210497B1 (ko) 1999-07-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee