DE69132676T2 - Verfahren zur Herstellung einer Halbleiteranordnung mit einem Graben für die Isolationkomponenten - Google Patents
Verfahren zur Herstellung einer Halbleiteranordnung mit einem Graben für die IsolationkomponentenInfo
- Publication number
- DE69132676T2 DE69132676T2 DE1991632676 DE69132676T DE69132676T2 DE 69132676 T2 DE69132676 T2 DE 69132676T2 DE 1991632676 DE1991632676 DE 1991632676 DE 69132676 T DE69132676 T DE 69132676T DE 69132676 T2 DE69132676 T2 DE 69132676T2
- Authority
- DE
- Germany
- Prior art keywords
- trench
- producing
- semiconductor device
- insulation components
- insulation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30608—Anisotropic liquid etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2135375A JP2667552B2 (ja) | 1990-05-28 | 1990-05-28 | 半導体装置の製造方法 |
JP2135374A JP2575520B2 (ja) | 1990-05-28 | 1990-05-28 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69132676D1 DE69132676D1 (de) | 2001-09-06 |
DE69132676T2 true DE69132676T2 (de) | 2002-06-13 |
Family
ID=26469233
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE1991632676 Expired - Fee Related DE69132676T2 (de) | 1990-05-28 | 1991-05-28 | Verfahren zur Herstellung einer Halbleiteranordnung mit einem Graben für die Isolationkomponenten |
Country Status (4)
Country | Link |
---|---|
US (3) | US5434447A (de) |
EP (1) | EP0459397B1 (de) |
KR (1) | KR960006714B1 (de) |
DE (1) | DE69132676T2 (de) |
Families Citing this family (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR960006714B1 (ko) * | 1990-05-28 | 1996-05-22 | 가부시끼가이샤 도시바 | 반도체 장치의 제조 방법 |
US5416041A (en) * | 1993-09-27 | 1995-05-16 | Siemens Aktiengesellschaft | Method for producing an insulating trench in an SOI substrate |
JP3396553B2 (ja) * | 1994-02-04 | 2003-04-14 | 三菱電機株式会社 | 半導体装置の製造方法及び半導体装置 |
US5705830A (en) * | 1996-09-05 | 1998-01-06 | Northrop Grumman Corporation | Static induction transistors |
JP3611226B2 (ja) * | 1996-09-17 | 2005-01-19 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
JP3547279B2 (ja) * | 1997-02-18 | 2004-07-28 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
TW388100B (en) | 1997-02-18 | 2000-04-21 | Hitachi Ulsi Eng Corp | Semiconductor deivce and process for producing the same |
CN1112727C (zh) * | 1997-02-18 | 2003-06-25 | 株式会社日立制作所 | 半导体器件及其制造工艺 |
DE19808514A1 (de) * | 1997-02-28 | 1998-09-10 | Int Rectifier Corp | Halbleiterbauteil sowie Verfahren zu seiner Herstellung |
US5880004A (en) * | 1997-06-10 | 1999-03-09 | Winbond Electronics Corp. | Trench isolation process |
US5801083A (en) * | 1997-10-20 | 1998-09-01 | Chartered Semiconductor Manufacturing, Ltd. | Use of polymer spacers for the fabrication of shallow trench isolation regions with rounded top corners |
US6103635A (en) * | 1997-10-28 | 2000-08-15 | Fairchild Semiconductor Corp. | Trench forming process and integrated circuit device including a trench |
US6180466B1 (en) * | 1997-12-18 | 2001-01-30 | Advanced Micro Devices, Inc. | Isotropic assisted dual trench etch |
DE19847455A1 (de) * | 1998-10-15 | 2000-04-27 | Bosch Gmbh Robert | Verfahren zur Bearbeitung von Silizium mittels Ätzprozessen |
JP2000164691A (ja) * | 1998-11-25 | 2000-06-16 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US6191447B1 (en) | 1999-05-28 | 2001-02-20 | Micro-Ohm Corporation | Power semiconductor devices that utilize tapered trench-based insulating regions to improve electric field profiles in highly doped drift region mesas and methods of forming same |
JP3917327B2 (ja) | 1999-06-01 | 2007-05-23 | 株式会社ルネサステクノロジ | 半導体装置の製造方法及び装置 |
US6461816B1 (en) * | 1999-07-09 | 2002-10-08 | Agilent Technologies, Inc. | Methods for controlling cross-hybridization in analysis of nucleic acid sequences |
US6623579B1 (en) * | 1999-11-02 | 2003-09-23 | Alien Technology Corporation | Methods and apparatus for fluidic self assembly |
US6479395B1 (en) * | 1999-11-02 | 2002-11-12 | Alien Technology Corporation | Methods for forming openings in a substrate and apparatuses with these openings and methods for creating assemblies with openings |
JP2001351895A (ja) | 2000-06-09 | 2001-12-21 | Denso Corp | 半導体装置の製造方法 |
US7078308B2 (en) | 2002-08-29 | 2006-07-18 | Micron Technology, Inc. | Method and apparatus for removing adjacent conductive and nonconductive materials of a microelectronic substrate |
US7129160B2 (en) | 2002-08-29 | 2006-10-31 | Micron Technology, Inc. | Method for simultaneously removing multiple conductive materials from microelectronic substrates |
US7153195B2 (en) | 2000-08-30 | 2006-12-26 | Micron Technology, Inc. | Methods and apparatus for selectively removing conductive material from a microelectronic substrate |
US7220166B2 (en) | 2000-08-30 | 2007-05-22 | Micron Technology, Inc. | Methods and apparatus for electromechanically and/or electrochemically-mechanically removing conductive material from a microelectronic substrate |
US6867448B1 (en) | 2000-08-31 | 2005-03-15 | Micron Technology, Inc. | Electro-mechanically polished structure |
TW512526B (en) * | 2000-09-07 | 2002-12-01 | Sanyo Electric Co | Semiconductor integrated circuit device and manufacturing method thereof |
US20030009294A1 (en) * | 2001-06-07 | 2003-01-09 | Jill Cheng | Integrated system for gene expression analysis |
KR100663662B1 (ko) * | 2001-06-21 | 2007-01-03 | 마이크론 테크놀로지 인코포레이티드 | 마이크로전자 기판으로부터 도전성 물질을 전기적, 기계적 및/또는 화학적으로 제거하기 위한 장치 및 방법 |
JP2003068751A (ja) * | 2001-08-27 | 2003-03-07 | Nec Yamagata Ltd | 半導体装置及びその製造方法 |
US7187139B2 (en) * | 2003-09-09 | 2007-03-06 | Microsemi Corporation | Split phase inverters for CCFL backlight system |
KR101085579B1 (ko) * | 2003-10-06 | 2011-11-25 | 마이크로세미 코포레이션 | 다수의 ccf 램프 동작을 위한 전류 공유 방법 및 장치 |
US7141933B2 (en) * | 2003-10-21 | 2006-11-28 | Microsemi Corporation | Systems and methods for a transformer configuration for driving multiple gas discharge tubes in parallel |
KR100545182B1 (ko) * | 2003-12-31 | 2006-01-24 | 동부아남반도체 주식회사 | 반도체 소자 및 그의 제조 방법 |
US7153777B2 (en) | 2004-02-20 | 2006-12-26 | Micron Technology, Inc. | Methods and apparatuses for electrochemical-mechanical polishing |
US7291541B1 (en) | 2004-03-18 | 2007-11-06 | National Semiconductor Corporation | System and method for providing improved trench isolation of semiconductor devices |
US7250731B2 (en) * | 2004-04-07 | 2007-07-31 | Microsemi Corporation | Primary side current balancing scheme for multiple CCF lamp operation |
US7566391B2 (en) | 2004-09-01 | 2009-07-28 | Micron Technology, Inc. | Methods and systems for removing materials from microfeature workpieces with organic and/or non-aqueous electrolytic media |
US7615479B1 (en) | 2004-11-08 | 2009-11-10 | Alien Technology Corporation | Assembly comprising functional block deposited therein |
US7262443B1 (en) * | 2004-12-29 | 2007-08-28 | T-Ram Semiconductor Inc. | Silicide uniformity for lateral bipolar transistors |
US7173382B2 (en) * | 2005-03-31 | 2007-02-06 | Microsemi Corporation | Nested balancing topology for balancing current among multiple lamps |
CN102087989A (zh) * | 2009-12-02 | 2011-06-08 | 无锡华润上华半导体有限公司 | 浅沟槽隔离结构的制造方法 |
CN102087990A (zh) * | 2009-12-07 | 2011-06-08 | 无锡华润上华半导体有限公司 | 浅沟槽隔离方法 |
CN107968050B (zh) * | 2017-11-24 | 2020-03-13 | 长江存储科技有限责任公司 | 沟道孔的底部刻蚀方法 |
CN112086351A (zh) * | 2019-06-13 | 2020-12-15 | 芯恩(青岛)集成电路有限公司 | 沟槽刻蚀方法 |
CN110993497A (zh) * | 2019-11-20 | 2020-04-10 | 上海华虹宏力半导体制造有限公司 | 沟槽顶部圆角化的方法 |
CN111106003A (zh) * | 2019-11-20 | 2020-05-05 | 上海华虹宏力半导体制造有限公司 | 沟槽顶部圆角化的方法 |
Family Cites Families (28)
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---|---|---|---|---|
JPS56103446A (en) * | 1980-01-22 | 1981-08-18 | Fujitsu Ltd | Semiconductor device |
JPS5712533A (en) * | 1980-06-26 | 1982-01-22 | Fujitsu Ltd | Manufacture of semiconductor device |
GB2126025B (en) * | 1982-08-14 | 1986-01-15 | Dresser Europe Sa | Power supply system and mining machine incorporating such system |
US4486266A (en) * | 1983-08-12 | 1984-12-04 | Tektronix, Inc. | Integrated circuit method |
JPH073858B2 (ja) * | 1984-04-11 | 1995-01-18 | 株式会社日立製作所 | 半導体装置の製造方法 |
FR2566179B1 (fr) * | 1984-06-14 | 1986-08-22 | Commissariat Energie Atomique | Procede d'autopositionnement d'un oxyde de champ localise par rapport a une tranchee d'isolement |
US4639288A (en) * | 1984-11-05 | 1987-01-27 | Advanced Micro Devices, Inc. | Process for formation of trench in integrated circuit structure using isotropic and anisotropic etching |
US4855017A (en) * | 1985-05-03 | 1989-08-08 | Texas Instruments Incorporated | Trench etch process for a single-wafer RIE dry etch reactor |
JPS6281727A (ja) * | 1985-10-05 | 1987-04-15 | Fujitsu Ltd | 埋込型素子分離溝の形成方法 |
US4653090A (en) * | 1985-12-16 | 1987-03-24 | American Telephone & Telegraph (At&T) | Graphics based call management |
JPS632371A (ja) * | 1986-06-23 | 1988-01-07 | Hitachi Ltd | 半導体装置 |
US4729815A (en) * | 1986-07-21 | 1988-03-08 | Motorola, Inc. | Multiple step trench etching process |
JPS6376330A (ja) * | 1986-09-18 | 1988-04-06 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JPS63181330A (ja) * | 1987-01-23 | 1988-07-26 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
FR2610141B1 (fr) * | 1987-01-26 | 1990-01-19 | Commissariat Energie Atomique | Circuit integre cmos et procede de fabrication de zones d'isolation electrique dans ce circuit |
JPS63234534A (ja) * | 1987-03-24 | 1988-09-29 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
JPS63314844A (ja) * | 1987-06-18 | 1988-12-22 | Toshiba Corp | 半導体装置の製造方法 |
JP2635607B2 (ja) * | 1987-08-28 | 1997-07-30 | 株式会社東芝 | 半導体装置の製造方法 |
US5258332A (en) * | 1987-08-28 | 1993-11-02 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor devices including rounding of corner portions by etching |
US4931409A (en) * | 1988-01-30 | 1990-06-05 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device having trench isolation |
US4876214A (en) * | 1988-06-02 | 1989-10-24 | Tektronix, Inc. | Method for fabricating an isolation region in a semiconductor substrate |
US5061653A (en) * | 1989-02-22 | 1991-10-29 | Texas Instruments Incorporated | Trench isolation process |
JP2757919B2 (ja) * | 1989-03-03 | 1998-05-25 | 三菱電機株式会社 | 半導体装置の製造方法 |
JPH03129854A (ja) * | 1989-10-16 | 1991-06-03 | Toshiba Corp | 半導体装置の製造方法 |
KR960006714B1 (ko) * | 1990-05-28 | 1996-05-22 | 가부시끼가이샤 도시바 | 반도체 장치의 제조 방법 |
US5106770A (en) * | 1990-11-16 | 1992-04-21 | Gte Laboratories Incorporated | Method of manufacturing semiconductor devices |
US5217919A (en) * | 1992-03-19 | 1993-06-08 | Harris Corporation | Method of forming island with polysilicon-filled trench isolation |
JP3311044B2 (ja) * | 1992-10-27 | 2002-08-05 | 株式会社東芝 | 半導体装置の製造方法 |
-
1991
- 1991-05-27 KR KR1019910008656A patent/KR960006714B1/ko not_active IP Right Cessation
- 1991-05-28 DE DE1991632676 patent/DE69132676T2/de not_active Expired - Fee Related
- 1991-05-28 EP EP91108691A patent/EP0459397B1/de not_active Expired - Lifetime
-
1994
- 1994-05-26 US US08/250,110 patent/US5434447A/en not_active Expired - Lifetime
-
1996
- 1996-08-30 US US08/705,705 patent/US5683908A/en not_active Expired - Lifetime
-
1997
- 1997-06-13 US US08/874,317 patent/US5858859A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE69132676D1 (de) | 2001-09-06 |
EP0459397B1 (de) | 2001-08-01 |
EP0459397A3 (de) | 1994-11-02 |
US5858859A (en) | 1999-01-12 |
EP0459397A2 (de) | 1991-12-04 |
US5683908A (en) | 1997-11-04 |
KR960006714B1 (ko) | 1996-05-22 |
US5434447A (en) | 1995-07-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |