DE69133178D1 - Verfahren zur Fertigung einer ROM-Speicherzelle mit einer niedrigen Drainkapazität und eine entsprechende ROM-Speicherzelle - Google Patents
Verfahren zur Fertigung einer ROM-Speicherzelle mit einer niedrigen Drainkapazität und eine entsprechende ROM-SpeicherzelleInfo
- Publication number
- DE69133178D1 DE69133178D1 DE69133178T DE69133178T DE69133178D1 DE 69133178 D1 DE69133178 D1 DE 69133178D1 DE 69133178 T DE69133178 T DE 69133178T DE 69133178 T DE69133178 T DE 69133178T DE 69133178 D1 DE69133178 D1 DE 69133178D1
- Authority
- DE
- Germany
- Prior art keywords
- memory cell
- rom memory
- manufacturing
- low drain
- drain capacity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/38—Doping programmed, e.g. mask ROM
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/38—Doping programmed, e.g. mask ROM
- H10B20/383—Channel doping programmed
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/38—Doping programmed, e.g. mask ROM
- H10B20/387—Source region or drain region doping programmed
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT19694A IT1239707B (it) | 1990-03-15 | 1990-03-15 | Processo per la realizzazione di una cella di memoria rom a bassa capacita' di drain |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69133178D1 true DE69133178D1 (de) | 2003-01-30 |
Family
ID=11160444
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69133178T Expired - Lifetime DE69133178D1 (de) | 1990-03-15 | 1991-03-07 | Verfahren zur Fertigung einer ROM-Speicherzelle mit einer niedrigen Drainkapazität und eine entsprechende ROM-Speicherzelle |
Country Status (5)
Country | Link |
---|---|
US (2) | US5328863A (de) |
EP (1) | EP0451883B1 (de) |
JP (1) | JPH05259412A (de) |
DE (1) | DE69133178D1 (de) |
IT (1) | IT1239707B (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1239707B (it) * | 1990-03-15 | 1993-11-15 | St Microelectrics Srl | Processo per la realizzazione di una cella di memoria rom a bassa capacita' di drain |
JP3202784B2 (ja) * | 1992-04-13 | 2001-08-27 | 三菱電機株式会社 | マスクrom半導体装置およびその製造方法 |
EP0575688B1 (de) * | 1992-06-26 | 1998-05-27 | STMicroelectronics S.r.l. | Programmierung von LDD-ROM-Zellen |
JP3221766B2 (ja) * | 1993-04-23 | 2001-10-22 | 三菱電機株式会社 | 電界効果トランジスタの製造方法 |
US5526306A (en) * | 1994-02-10 | 1996-06-11 | Mega Chips Corporation | Semiconductor memory device and method of fabricating the same |
JP3337578B2 (ja) * | 1994-11-29 | 2002-10-21 | 三菱電機システムエル・エス・アイ・デザイン株式会社 | 半導体装置およびその製造方法 |
US5790452A (en) * | 1996-05-02 | 1998-08-04 | Integrated Device Technology, Inc. | Memory cell having asymmetrical source/drain pass transistors and method for operating same |
US6027978A (en) * | 1997-01-28 | 2000-02-22 | Advanced Micro Devices, Inc. | Method of making an IGFET with a non-uniform lateral doping profile in the channel region |
DE69841732D1 (de) * | 1997-05-13 | 2010-08-05 | St Microelectronics Srl | Verfahren zur selektiven Herstellung von Salizid über aktiven Oberflächen von MOS-Vorrichtungen |
JP5179692B2 (ja) * | 2002-08-30 | 2013-04-10 | 富士通セミコンダクター株式会社 | 半導体記憶装置及びその製造方法 |
Family Cites Families (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4059826A (en) * | 1975-12-29 | 1977-11-22 | Texas Instruments Incorporated | Semiconductor memory array with field effect transistors programmable by alteration of threshold voltage |
US4225875A (en) * | 1978-04-19 | 1980-09-30 | Rca Corporation | Short channel MOS devices and the method of manufacturing same |
US4208780A (en) * | 1978-08-03 | 1980-06-24 | Rca Corporation | Last-stage programming of semiconductor integrated circuits including selective removal of passivation layer |
US4514897A (en) * | 1979-09-04 | 1985-05-07 | Texas Instruments Incorporated | Electrically programmable floating gate semiconductor memory device |
US4376947A (en) * | 1979-09-04 | 1983-03-15 | Texas Instruments Incorporated | Electrically programmable floating gate semiconductor memory device |
JPS583192A (ja) * | 1981-06-30 | 1983-01-08 | Fujitsu Ltd | 読み出し専用メモリ |
US4599118A (en) * | 1981-12-30 | 1986-07-08 | Mostek Corporation | Method of making MOSFET by multiple implantations followed by a diffusion step |
US5141890A (en) * | 1982-02-01 | 1992-08-25 | Texas Instruments Incorporated | CMOS sidewall oxide-lightly doped drain process |
JPS58148448A (ja) * | 1982-03-01 | 1983-09-03 | Nippon Denso Co Ltd | 半導体romの製造方法 |
US4536944A (en) * | 1982-12-29 | 1985-08-27 | International Business Machines Corporation | Method of making ROM/PLA semiconductor device by late stage personalization |
JPH0626246B2 (ja) * | 1983-06-17 | 1994-04-06 | 株式会社日立製作所 | 半導体メモリの製造方法 |
US4513494A (en) * | 1983-07-19 | 1985-04-30 | American Microsystems, Incorporated | Late mask process for programming read only memories |
US4698787A (en) * | 1984-11-21 | 1987-10-06 | Exel Microelectronics, Inc. | Single transistor electrically programmable memory device and method |
US4649638A (en) * | 1985-04-17 | 1987-03-17 | International Business Machines Corp. | Construction of short-length electrode in semiconductor device |
US4649629A (en) * | 1985-07-29 | 1987-03-17 | Thomson Components - Mostek Corp. | Method of late programming a read only memory |
US4956308A (en) * | 1987-01-20 | 1990-09-11 | Itt Corporation | Method of making self-aligned field-effect transistor |
IT1186430B (it) * | 1985-12-12 | 1987-11-26 | Sgs Microelettrica Spa | Rpocedimento per la realizzazione di memorie a sola lettura in tecnologia nmos programmate mediante impiantazione ionica e memoria a sola lettura ottenuta mediante tale procedimento |
US4805143A (en) * | 1986-01-16 | 1989-02-14 | Hitachi Ltd. | Read-only memory |
JPS6364361A (ja) * | 1986-09-03 | 1988-03-22 | Sharp Corp | マスクromの製造方法 |
US5024960A (en) * | 1987-06-16 | 1991-06-18 | Texas Instruments Incorporated | Dual LDD submicron CMOS process for making low and high voltage transistors with common gate |
US4852062A (en) * | 1987-09-28 | 1989-07-25 | Motorola, Inc. | EPROM device using asymmetrical transistor characteristics |
JPH02355A (ja) * | 1987-12-15 | 1990-01-05 | Seiko Epson Corp | 半導体記憶装置 |
IT1217372B (it) * | 1988-03-28 | 1990-03-22 | Sgs Thomson Microelectronics | Procedimento per la programmazione di memorie rom in tecnologia mos ecmos |
JPH0748503B2 (ja) * | 1988-11-29 | 1995-05-24 | 三菱電機株式会社 | 電界効果トランジスタの製造方法 |
US4874713A (en) * | 1989-05-01 | 1989-10-17 | Ncr Corporation | Method of making asymmetrically optimized CMOS field effect transistors |
JPH0821687B2 (ja) * | 1989-05-31 | 1996-03-04 | 富士通株式会社 | 半導体装置及びその製造方法 |
EP0416141A1 (de) * | 1989-09-04 | 1991-03-13 | Siemens Aktiengesellschaft | Verfahren zur Herstellung eines FET mit asymmetrisch angeordnetem Gate-Bereich |
IT1239707B (it) * | 1990-03-15 | 1993-11-15 | St Microelectrics Srl | Processo per la realizzazione di una cella di memoria rom a bassa capacita' di drain |
KR930000581B1 (ko) * | 1990-04-04 | 1993-01-25 | 금성일렉트론 주식회사 | 자기 정렬된 캐패시터 콘택을 갖는 셀 제조방법 및 구조 |
US5032881A (en) * | 1990-06-29 | 1991-07-16 | National Semiconductor Corporation | Asymmetric virtual ground EPROM cell and fabrication method |
US5117389A (en) * | 1990-09-05 | 1992-05-26 | Macronix International Co., Ltd. | Flat-cell read-only-memory integrated circuit |
US5200802A (en) * | 1991-05-24 | 1993-04-06 | National Semiconductor Corporation | Semiconductor ROM cell programmed using source mask |
-
1990
- 1990-03-15 IT IT19694A patent/IT1239707B/it active IP Right Grant
-
1991
- 1991-03-07 EP EP91200496A patent/EP0451883B1/de not_active Expired - Lifetime
- 1991-03-07 DE DE69133178T patent/DE69133178D1/de not_active Expired - Lifetime
- 1991-03-13 US US07/668,873 patent/US5328863A/en not_active Expired - Lifetime
- 1991-03-13 JP JP3048173A patent/JPH05259412A/ja active Pending
-
1994
- 1994-03-17 US US08/210,595 patent/US5732012A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
IT9019694A1 (it) | 1991-09-15 |
US5732012A (en) | 1998-03-24 |
EP0451883B1 (de) | 2002-12-18 |
IT1239707B (it) | 1993-11-15 |
US5328863A (en) | 1994-07-12 |
JPH05259412A (ja) | 1993-10-08 |
EP0451883A1 (de) | 1991-10-16 |
IT9019694A0 (it) | 1990-03-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de |