DE69211741T2 - Prüfsignalausgangsschaltung für LSI - Google Patents

Prüfsignalausgangsschaltung für LSI

Info

Publication number: DE69211741T2
Authority: DE; Germany
Prior art keywords: lsi; signal output; output circuit; test signal; test
Prior art date: 1991-03-27
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

DE69211741T

Other languages

English (en)

Other versions

DE69211741D1 (de

Inventor

Hitoshi Yamahata

Masahiro Kusuda

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

NEC Corp

Original Assignee

NEC Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1991-03-27

Filing date

1992-03-27

Publication date

1996-10-24

1992-03-27 Application filed by NEC Corp filed Critical NEC Corp

1996-08-01 Application granted granted Critical

1996-08-01 Publication of DE69211741D1 publication Critical patent/DE69211741D1/de

1996-10-24 Publication of DE69211741T2 publication Critical patent/DE69211741T2/de

2012-03-28 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Links

Classifications

- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode

DE69211741T 1991-03-27 1992-03-27 Prüfsignalausgangsschaltung für LSI Expired - Fee Related DE69211741T2 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
JP6229291		1991-03-27

Publications (2)

Publication Number	Publication Date
DE69211741D1 DE69211741D1 (de)	1996-08-01
DE69211741T2 true DE69211741T2 (de)	1996-10-24

Family

ID=13195898

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE69211741T Expired - Fee Related DE69211741T2 (de)	1991-03-27	1992-03-27	Prüfsignalausgangsschaltung für LSI

Country Status (5)

Country	Link
US (1)	US5379300A (de)
EP (1)	EP0506462B1 (de)
JP (1)	JPH05302961A (de)
KR (1)	KR960003364B1 (de)
DE (1)	DE69211741T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPH0779155A (ja) *	1993-09-06	1995-03-20	Mitsubishi Electric Corp	信号選択装置
JPH07167920A (ja) *	1993-10-18	1995-07-04	Fujitsu Ltd	Ｌｓｉ
US5726995A (en) *	1994-12-15	1998-03-10	Intel Corporation	Method and apparatus for selecting modes of an intergrated circuit
US5869979A (en) *	1996-04-05	1999-02-09	Altera Corporation	Technique for preconditioning I/Os during reconfiguration
US6260163B1 (en)	1997-12-12	2001-07-10	International Business Machines Corporation	Testing high I/O integrated circuits on a low I/O tester
JPH11231967A (ja)	1998-02-17	1999-08-27	Nec Corp	クロック出力回路
KR100400957B1 (ko)	1999-07-29	2003-10-10	마쯔시다덴기산교 가부시키가이샤	집적회로 내부신호 감시장치
JP2002340978A (ja)	2001-05-10	2002-11-27	Canon Inc	出力制御回路および出力制御方法
KR100512175B1 (ko) *	2003-03-17	2005-09-02	삼성전자주식회사	출력 신호들을 선택적으로 출력가능한 반도체 집적 회로및 그것의 테스트 방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS62250593A (ja) *	1986-04-23	1987-10-31	Hitachi Ltd	ダイナミツク型ｒａｍ
US4710927A (en) *	1986-07-24	1987-12-01	Integrated Device Technology, Inc.	Diagnostic circuit
US5012180A (en) *	1988-05-17	1991-04-30	Zilog, Inc.	System for testing internal nodes
US4975641A (en) *	1988-07-14	1990-12-04	Sharp Kabushiki Kaisha	Integrated circuit and method for testing the integrated circuit
US4980889A (en) *	1988-12-29	1990-12-25	Deguise Wayne J	Multi-mode testing systems
JPH02181677A (ja) *	1989-01-06	1990-07-16	Sharp Corp	Ｌｓｉのテストモード切替方式
US5001713A (en) *	1989-02-08	1991-03-19	Texas Instruments Incorporated	Event qualified testing architecture for integrated circuits
EP0403821B1 (de) *	1989-05-31	1995-02-01	Fujitsu Limited	Integrierte Halbleiterschaltungsanordnung mit Testschaltung
US5072447A (en) *	1989-11-08	1991-12-10	National Semiconductor Corporation	Pattern injector
JPH03252569A (ja) *	1990-02-26	1991-11-11	Advanced Micro Devicds Inc	スキャンパス用レジスタ回路
JP2561164B2 (ja) *	1990-02-26	1996-12-04	三菱電機株式会社	半導体集積回路

1992
- 1992-03-03 JP JP4045084A patent/JPH05302961A/ja not_active Withdrawn
- 1992-03-27 KR KR1019920005042A patent/KR960003364B1/ko not_active IP Right Cessation
- 1992-03-27 US US07/858,614 patent/US5379300A/en not_active Expired - Fee Related
- 1992-03-27 DE DE69211741T patent/DE69211741T2/de not_active Expired - Fee Related
- 1992-03-27 EP EP92302717A patent/EP0506462B1/de not_active Expired - Lifetime

Also Published As

Publication number	Publication date
KR920018774A (ko)	1992-10-22
EP0506462B1 (de)	1996-06-26
KR960003364B1 (ko)	1996-03-09
EP0506462A3 (en)	1993-05-12
EP0506462A2 (de)	1992-09-30
US5379300A (en)	1995-01-03
DE69211741D1 (de)	1996-08-01
JPH05302961A (ja)	1993-11-16

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Legal Events

Date	Code	Title	Description
1997-07-24	8364	No opposition during term of opposition
1998-03-12	8339	Ceased/non-payment of the annual fee