DE69215574D1 - Integrierte Halbleiterschaltung mit geräuscharmen Ausgangspuffern - Google Patents

Integrierte Halbleiterschaltung mit geräuscharmen Ausgangspuffern

Info

Publication number
DE69215574D1
DE69215574D1 DE69215574T DE69215574T DE69215574D1 DE 69215574 D1 DE69215574 D1 DE 69215574D1 DE 69215574 T DE69215574 T DE 69215574T DE 69215574 T DE69215574 T DE 69215574T DE 69215574 D1 DE69215574 D1 DE 69215574D1
Authority
DE
Germany
Prior art keywords
low
semiconductor circuit
integrated semiconductor
output buffers
noise output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69215574T
Other languages
English (en)
Other versions
DE69215574T2 (de
Inventor
Satoru Tanoi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of DE69215574D1 publication Critical patent/DE69215574D1/de
Application granted granted Critical
Publication of DE69215574T2 publication Critical patent/DE69215574T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
    • H03K17/166—Soft switching
    • H03K17/167—Soft switching using parallel switching arrangements
DE69215574T 1991-04-15 1992-04-15 Integrierte Halbleiterschaltung mit geräuscharmen Ausgangspuffern Expired - Fee Related DE69215574T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3082709A JP2930440B2 (ja) 1991-04-15 1991-04-15 半導体集積回路

Publications (2)

Publication Number Publication Date
DE69215574D1 true DE69215574D1 (de) 1997-01-16
DE69215574T2 DE69215574T2 (de) 1997-06-12

Family

ID=13781934

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69215574T Expired - Fee Related DE69215574T2 (de) 1991-04-15 1992-04-15 Integrierte Halbleiterschaltung mit geräuscharmen Ausgangspuffern

Country Status (5)

Country Link
US (1) US5237213A (de)
EP (1) EP0509489B1 (de)
JP (1) JP2930440B2 (de)
KR (1) KR920020707A (de)
DE (1) DE69215574T2 (de)

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US5598119A (en) * 1995-04-05 1997-01-28 Hewlett-Packard Company Method and apparatus for a load adaptive pad driver
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US5760633A (en) * 1995-06-08 1998-06-02 International Business Machines Corporation Low power low noise circuit design using half Vdd
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KR0172238B1 (ko) * 1995-06-30 1999-03-30 김주용 멀티-비트 데이타 출력 완충장치
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US6472917B2 (en) * 1997-03-19 2002-10-29 Hitachi, Ltd. Semiconductor integrated circuit device having compensation for wiring distance delays
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US6768165B1 (en) 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6114895A (en) * 1997-10-29 2000-09-05 Agilent Technologies Integrated circuit assembly having output pads with application specific characteristics and method of operation
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US6307399B1 (en) * 1998-06-02 2001-10-23 Integrated Device Technology, Inc. High speed buffer circuit with improved noise immunity
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US6356102B1 (en) 1998-11-13 2002-03-12 Integrated Device Technology, Inc. Integrated circuit output buffers having control circuits therein that utilize output signal feedback to control pull-up and pull-down time intervals
US6242942B1 (en) 1998-11-13 2001-06-05 Integrated Device Technology, Inc. Integrated circuit output buffers having feedback switches therein for reducing simultaneous switching noise and improving impedance matching characteristics
US6091260A (en) * 1998-11-13 2000-07-18 Integrated Device Technology, Inc. Integrated circuit output buffers having low propagation delay and improved noise characteristics
JP3239357B2 (ja) * 1999-01-29 2001-12-17 日本電気株式会社 チャージポンプ回路
JP3499157B2 (ja) * 1999-06-15 2004-02-23 日本テキサス・インスツルメンツ株式会社 クランプ回路及びそれを用いたインターフェース回路
US6373295B2 (en) * 1999-06-21 2002-04-16 Semiconductor Components Industries Llc Rail-to-rail driver for use in a regulator, and method
US6441643B1 (en) * 2000-02-28 2002-08-27 International Business Machines Corporation Method and apparatus for driving multiple voltages
JP3888019B2 (ja) * 2000-02-28 2007-02-28 ヤマハ株式会社 出力バッファ回路
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US6700818B2 (en) 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US20040151032A1 (en) * 2003-01-30 2004-08-05 Yan Polansky High speed and low noise output buffer
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US6774676B1 (en) * 2003-02-24 2004-08-10 National Semiconductor Corporation Dual threshold buffer with hysteresis
US7142464B2 (en) 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
US7123532B2 (en) 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
WO2005094178A2 (en) 2004-04-01 2005-10-13 Saifun Semiconductors Ltd. Method, circuit and systems for erasing one or more non-volatile memory cells
US7317633B2 (en) 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
US7095655B2 (en) * 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7535765B2 (en) 2004-12-09 2009-05-19 Saifun Semiconductors Ltd. Non-volatile memory device and method for reading cells
CN1838323A (zh) 2005-01-19 2006-09-27 赛芬半导体有限公司 可预防固定模式编程的方法
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US8400841B2 (en) 2005-06-15 2013-03-19 Spansion Israel Ltd. Device to program adjacent storage cells of different NROM cells
US7184313B2 (en) 2005-06-17 2007-02-27 Saifun Semiconductors Ltd. Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells
DE102005030886B3 (de) * 2005-07-01 2007-02-08 Infineon Technologies Ag Schaltungsanordnung mit einem Transistorbauelement und einem Freilaufelement
US7786512B2 (en) 2005-07-18 2010-08-31 Saifun Semiconductors Ltd. Dense non-volatile memory array and method of fabrication
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US7221138B2 (en) 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
US7352627B2 (en) 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7638835B2 (en) 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
KR100776751B1 (ko) * 2006-06-09 2007-11-19 주식회사 하이닉스반도체 전압 공급 장치 및 방법
US7605579B2 (en) 2006-09-18 2009-10-20 Saifun Semiconductors Ltd. Measuring and controlling current consumption and output current of charge pumps
JP2008263446A (ja) * 2007-04-12 2008-10-30 Matsushita Electric Ind Co Ltd 出力回路
US9252764B1 (en) * 2013-03-12 2016-02-02 Cirrus Logic, Inc. Systems and methods for reducing spike voltages in a switched output stage
US8872561B2 (en) 2013-03-14 2014-10-28 Cirrus Logic, Inc. Systems and methods for edge control based on detecting current direction in a switched output stage
US8970258B2 (en) 2013-03-14 2015-03-03 Cirrus Logic, Inc. Systems and methods for edge control in a switched output stage
US9847706B2 (en) 2013-03-14 2017-12-19 Cirrus Logic, Inc. Systems and methods for reducing voltage ringing in a power converter

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Also Published As

Publication number Publication date
US5237213A (en) 1993-08-17
KR920020707A (ko) 1992-11-21
EP0509489A1 (de) 1992-10-21
EP0509489B1 (de) 1996-12-04
DE69215574T2 (de) 1997-06-12
JP2930440B2 (ja) 1999-08-03
JPH04315316A (ja) 1992-11-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee