DE69220995D1 - Metallisierung eines integrierten Schaltkreises mit Nullkontaktanforderung des Gehäuses und Verfahren zu seiner Herstellung - Google Patents

Metallisierung eines integrierten Schaltkreises mit Nullkontaktanforderung des Gehäuses und Verfahren zu seiner Herstellung

Info

Publication number
DE69220995D1
DE69220995D1 DE69220995T DE69220995T DE69220995D1 DE 69220995 D1 DE69220995 D1 DE 69220995D1 DE 69220995 T DE69220995 T DE 69220995T DE 69220995 T DE69220995 T DE 69220995T DE 69220995 D1 DE69220995 D1 DE 69220995D1
Authority
DE
Germany
Prior art keywords
metallization
manufacture
housing
integrated circuit
zero contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69220995T
Other languages
English (en)
Other versions
DE69220995T2 (de
Inventor
Fusen E Chen
Fu-Tai Liou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Publication of DE69220995D1 publication Critical patent/DE69220995D1/de
Application granted granted Critical
Publication of DE69220995T2 publication Critical patent/DE69220995T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material
DE69220995T 1991-03-27 1992-03-26 Metallisierung eines integrierten Schaltkreises mit Nullkontaktanforderung des Gehäuses und Verfahren zu seiner Herstellung Expired - Fee Related DE69220995T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/676,084 US5270254A (en) 1991-03-27 1991-03-27 Integrated circuit metallization with zero contact enclosure requirements and method of making the same

Publications (2)

Publication Number Publication Date
DE69220995D1 true DE69220995D1 (de) 1997-09-04
DE69220995T2 DE69220995T2 (de) 1997-12-11

Family

ID=24713160

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69220995T Expired - Fee Related DE69220995T2 (de) 1991-03-27 1992-03-26 Metallisierung eines integrierten Schaltkreises mit Nullkontaktanforderung des Gehäuses und Verfahren zu seiner Herstellung

Country Status (5)

Country Link
US (2) US5270254A (de)
EP (1) EP0506426B1 (de)
JP (1) JPH05114587A (de)
KR (1) KR920018921A (de)
DE (1) DE69220995T2 (de)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5514624A (en) * 1990-08-07 1996-05-07 Seiko Epson Corporation Method of manufacturing a microelectronic interlayer dielectric structure
US5270254A (en) * 1991-03-27 1993-12-14 Sgs-Thomson Microelectronics, Inc. Integrated circuit metallization with zero contact enclosure requirements and method of making the same
JP2946978B2 (ja) * 1991-11-29 1999-09-13 ソニー株式会社 配線形成方法
US6051490A (en) * 1991-11-29 2000-04-18 Sony Corporation Method of forming wirings
GB9219281D0 (en) * 1992-09-11 1992-10-28 Inmos Ltd Manufacture of semiconductor devices
GB9219267D0 (en) * 1992-09-11 1992-10-28 Inmos Ltd Manufacture of semiconductor devices
KR960002061B1 (ko) * 1992-10-05 1996-02-10 삼성전자주식회사 반도체 장치의 배선층 형성방법
KR100320364B1 (ko) * 1993-03-23 2002-04-22 가와사키 마이크로 엘렉트로닉스 가부시키가이샤 금속배선및그의형성방법
JP3401843B2 (ja) * 1993-06-21 2003-04-28 ソニー株式会社 半導体装置における多層配線の形成方法
US5652180A (en) * 1993-06-28 1997-07-29 Kawasaki Steel Corporation Method of manufacturing semiconductor device with contact structure
EP0645621A3 (de) * 1993-09-28 1995-11-08 Siemens Ag Sensoranordnung.
JPH07130852A (ja) * 1993-11-02 1995-05-19 Sony Corp 金属配線材料の形成方法
EP0660393B1 (de) * 1993-12-23 2000-05-10 STMicroelectronics, Inc. Verfahren und Dielektrikumstruktur zur Erleichterung der Metallüberätzung ohne Beschädigung des Zwischendielektrikums
US5545590A (en) * 1994-08-29 1996-08-13 International Business Machines Corporation Conductive rie-resistant collars for studs beneath rie-defined wires
JP2701751B2 (ja) * 1994-08-30 1998-01-21 日本電気株式会社 半導体装置の製造方法
TW290717B (en) * 1994-10-28 1996-11-11 Advanced Micro Devices Inc Method to prevent formation of defects during multilayer interconnect processing
US5691571A (en) * 1994-12-28 1997-11-25 Nec Corporation Semiconductor device having fine contact hole with high aspect ratio
DE69533823D1 (de) * 1994-12-29 2005-01-05 St Microelectronics Inc Elektrische Verbindungsstruktur auf einer integrierten Schaltungsanordnung mit einem Zapfen mit vergrössertem Kopf
DE69527344T2 (de) * 1994-12-29 2003-02-27 St Microelectronics Inc Verfahren zur Herstellung einer Halbleiterverbindungsstruktur
US6001729A (en) * 1995-01-10 1999-12-14 Kawasaki Steel Corporation Method of forming wiring structure for semiconductor device
JPH08191054A (ja) * 1995-01-10 1996-07-23 Kawasaki Steel Corp 半導体装置及びその製造方法
KR100425655B1 (ko) * 1995-03-28 2004-06-26 텍사스 인스트루먼츠 인코포레이티드 집적회로의금속화층사이의반응을최소화하기위한확산방지삼중층및제조방법
US6191484B1 (en) 1995-07-28 2001-02-20 Stmicroelectronics, Inc. Method of forming planarized multilevel metallization in an integrated circuit
US5641992A (en) * 1995-08-10 1997-06-24 Siemens Components, Inc. Metal interconnect structure for an integrated circuit with improved electromigration reliability
US6111319A (en) * 1995-12-19 2000-08-29 Stmicroelectronics, Inc. Method of forming submicron contacts and vias in an integrated circuit
US5847460A (en) * 1995-12-19 1998-12-08 Stmicroelectronics, Inc. Submicron contacts and vias in an integrated circuit
US5851923A (en) * 1996-01-18 1998-12-22 Micron Technology, Inc. Integrated circuit and method for forming and integrated circuit
KR100215846B1 (ko) * 1996-05-16 1999-08-16 구본준 반도체장치의 배선형성방법
US7943505B2 (en) * 1997-03-14 2011-05-17 Micron Technology, Inc. Advanced VLSI metallization
US5911113A (en) 1997-03-18 1999-06-08 Applied Materials, Inc. Silicon-doped titanium wetting layer for aluminum plug
JP3725964B2 (ja) * 1997-04-17 2005-12-14 株式会社ルネサステクノロジ 半導体装置及び半導体装置の製造方法
JP3381767B2 (ja) * 1997-09-22 2003-03-04 東京エレクトロン株式会社 成膜方法および半導体装置の製造方法
US5981395A (en) * 1997-10-18 1999-11-09 United Microelectronics Corp. Method of fabricating an unlanded metal via of multi-level interconnection
US6020266A (en) * 1997-12-31 2000-02-01 Intel Corporation Single step electroplating process for interconnect via fill and metal line patterning
FR2774811B1 (fr) * 1998-02-10 2003-05-09 Sgs Thomson Microelectronics Procede de formation de lignes conductrices sur des circuits integres
TW407342B (en) * 1998-06-17 2000-10-01 United Microelectronics Corp Planarization method of damascene structure
JP3266109B2 (ja) * 1998-08-05 2002-03-18 株式会社村田製作所 電子デバイスの作製方法
US6177353B1 (en) * 1998-09-15 2001-01-23 Infineon Technologies North America Corp. Metallization etching techniques for reducing post-etch corrosion of metal lines
US6724088B1 (en) * 1999-04-20 2004-04-20 International Business Machines Corporation Quantum conductive barrier for contact to shallow diffusion region
JP4288767B2 (ja) * 1999-07-07 2009-07-01 東京エレクトロン株式会社 半導体装置の製造方法
US6566759B1 (en) 1999-08-23 2003-05-20 International Business Machines Corporation Self-aligned contact areas for sidewall image transfer formed conductors
KR100625388B1 (ko) * 2000-04-04 2006-09-18 주식회사 하이닉스반도체 반도체소자의 금속배선 형성방법
US6489237B1 (en) * 2001-12-04 2002-12-03 Taiwan Semiconductor Manufacturing Company Method of patterning lines in semiconductor devices
KR100625393B1 (ko) * 2004-01-05 2006-09-19 주식회사 하이닉스반도체 반도체소자의 제조방법
KR100641980B1 (ko) * 2004-12-17 2006-11-02 동부일렉트로닉스 주식회사 반도체 소자의 배선 및 그 형성방법
TWI254352B (en) * 2005-06-20 2006-05-01 Macronix Int Co Ltd Method of fabricating conductive lines and structure of the same
US9006801B2 (en) * 2011-01-25 2015-04-14 International Business Machines Corporation Method for forming metal semiconductor alloys in contact holes and trenches
US9922876B1 (en) * 2017-01-24 2018-03-20 Macronix International Co., Ltd. Interconnect structure and fabricating method thereof
CN108346616B (zh) * 2017-01-25 2021-03-05 旺宏电子股份有限公司 内连线结构及其制造方法
KR20210154294A (ko) * 2020-06-11 2021-12-21 삼성전자주식회사 반도체 장치 및 그 제조 방법

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4835778A (de) * 1971-09-09 1973-05-26
JPS5319774A (en) * 1976-08-06 1978-02-23 Seiko Epson Corp Semiconductor integrated circuit
JPS5643742A (en) * 1979-09-17 1981-04-22 Mitsubishi Electric Corp Manufacture of semiconductor
JPS5750429A (en) * 1980-09-12 1982-03-24 Nec Corp Manufacture of semiconductor device
US4720908A (en) * 1984-07-11 1988-01-26 Texas Instruments Incorporated Process for making contacts and interconnects for holes having vertical sidewalls
US4656732A (en) * 1984-09-26 1987-04-14 Texas Instruments Incorporated Integrated circuit fabrication process
US4677739A (en) * 1984-11-29 1987-07-07 Texas Instruments Incorporated High density CMOS integrated circuit manufacturing process
JPS62133713A (ja) * 1985-12-06 1987-06-16 Hitachi Ltd 電極形成方法およびその電極
US4924295A (en) * 1986-11-28 1990-05-08 Siemens Aktiengesellschaft Integrated semi-conductor circuit comprising at least two metallization levels composed of aluminum or aluminum compounds and a method for the manufacture of same
US4960732A (en) * 1987-02-19 1990-10-02 Advanced Micro Devices, Inc. Contact plug and interconnect employing a barrier lining and a backfilled conductor material
US4884123A (en) * 1987-02-19 1989-11-28 Advanced Micro Devices, Inc. Contact plug and interconnect employing a barrier lining and a backfilled conductor material
JPS63275113A (ja) * 1987-05-07 1988-11-11 Nec Corp 半導体装置の製造方法
US4994410A (en) * 1988-04-04 1991-02-19 Motorola, Inc. Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process
US4837183A (en) * 1988-05-02 1989-06-06 Motorola Inc. Semiconductor device metallization process
FR2634317A1 (fr) * 1988-07-12 1990-01-19 Philips Nv Procede pour fabriquer un dispositif semiconducteur ayant au moins un niveau de prise de contact a travers des ouvertures de contact de petites dimensions
JPH02231712A (ja) * 1989-03-03 1990-09-13 Mitsubishi Electric Corp 半導体装置の製造方法
EP0388563B1 (de) * 1989-03-24 1994-12-14 STMicroelectronics, Inc. Verfahren zum Herstellen eines Kontaktes/VIA
US5270254A (en) * 1991-03-27 1993-12-14 Sgs-Thomson Microelectronics, Inc. Integrated circuit metallization with zero contact enclosure requirements and method of making the same

Also Published As

Publication number Publication date
US5371410A (en) 1994-12-06
JPH05114587A (ja) 1993-05-07
KR920018921A (ko) 1992-10-22
EP0506426A1 (de) 1992-09-30
EP0506426B1 (de) 1997-07-23
DE69220995T2 (de) 1997-12-11
US5270254A (en) 1993-12-14

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