DE69225520D1 - Gegenstand, beinhaltend eine in Gitterschichten fehlangepasste Halbleiter-Heterostruktur - Google Patents

Gegenstand, beinhaltend eine in Gitterschichten fehlangepasste Halbleiter-Heterostruktur

Info

Publication number
DE69225520D1
DE69225520D1 DE69225520T DE69225520T DE69225520D1 DE 69225520 D1 DE69225520 D1 DE 69225520D1 DE 69225520 T DE69225520 T DE 69225520T DE 69225520 T DE69225520 T DE 69225520T DE 69225520 D1 DE69225520 D1 DE 69225520D1
Authority
DE
Germany
Prior art keywords
mismatched
object including
semiconductor heterostructure
lattice layers
lattice
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69225520T
Other languages
English (en)
Other versions
DE69225520T2 (de
Inventor
John Condon Bean
Gregg Sumio Higashi
Robert Hull
Justin Larry Peticolas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Publication of DE69225520D1 publication Critical patent/DE69225520D1/de
Application granted granted Critical
Publication of DE69225520T2 publication Critical patent/DE69225520T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
DE69225520T 1991-03-18 1992-03-12 Gegenstand, beinhaltend eine in Gitterschichten fehlangepasste Halbleiter-Heterostruktur Expired - Lifetime DE69225520T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/671,276 US5091767A (en) 1991-03-18 1991-03-18 Article comprising a lattice-mismatched semiconductor heterostructure

Publications (2)

Publication Number Publication Date
DE69225520D1 true DE69225520D1 (de) 1998-06-25
DE69225520T2 DE69225520T2 (de) 1998-10-01

Family

ID=24693839

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69225520T Expired - Lifetime DE69225520T2 (de) 1991-03-18 1992-03-12 Gegenstand, beinhaltend eine in Gitterschichten fehlangepasste Halbleiter-Heterostruktur

Country Status (4)

Country Link
US (1) US5091767A (de)
EP (1) EP0505093B1 (de)
JP (1) JP3027473B2 (de)
DE (1) DE69225520T2 (de)

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US6703688B1 (en) * 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
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US7335545B2 (en) * 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US20030227057A1 (en) * 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US7307273B2 (en) * 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US6946371B2 (en) * 2002-06-10 2005-09-20 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
US6982474B2 (en) * 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
WO2004012243A2 (en) * 2002-07-29 2004-02-05 Amberwave Systems Selective placement of dislocation arrays
US7049627B2 (en) 2002-08-23 2006-05-23 Amberwave Systems Corporation Semiconductor heterostructures and related methods
US7594967B2 (en) * 2002-08-30 2009-09-29 Amberwave Systems Corporation Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy
JP4659732B2 (ja) * 2003-01-27 2011-03-30 台湾積體電路製造股▲ふん▼有限公司 半導体層を形成する方法
CN100437970C (zh) * 2003-03-07 2008-11-26 琥珀波系统公司 一种结构及用于形成半导体结构的方法
GB2418531A (en) * 2004-09-22 2006-03-29 Univ Warwick Formation of lattice-tuning semiconductor substrates
US7393733B2 (en) * 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
FI20045482A0 (fi) 2004-12-14 2004-12-14 Optogan Oy Matalamman dislokaatiotiheyden omaava puolijohdesubstraatti, ja menetelmä sen valmistamiseksi
DE102005000826A1 (de) * 2005-01-05 2006-07-20 Siltronic Ag Halbleiterscheibe mit Silicium-Germanium-Schicht und Verfahren zu deren Herstellung
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WO2006125040A2 (en) * 2005-05-17 2006-11-23 Amberwave Systems Corporation Lattice-mismatched semiconductor structures with reduced dislocation defect densities related methods for device fabrication
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US7626246B2 (en) * 2005-07-26 2009-12-01 Amberwave Systems Corporation Solutions for integrated circuit integration of alternative active area materials
US20070054467A1 (en) * 2005-09-07 2007-03-08 Amberwave Systems Corporation Methods for integrating lattice-mismatched semiconductor structure on insulators
US7638842B2 (en) * 2005-09-07 2009-12-29 Amberwave Systems Corporation Lattice-mismatched semiconductor structures on insulators
US7777250B2 (en) * 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
WO2008030574A1 (en) 2006-09-07 2008-03-13 Amberwave Systems Corporation Defect reduction using aspect ratio trapping
WO2008036256A1 (en) * 2006-09-18 2008-03-27 Amberwave Systems Corporation Aspect ratio trapping for mixed signal applications
WO2008039534A2 (en) 2006-09-27 2008-04-03 Amberwave Systems Corporation Quantum tunneling devices and circuits with lattice- mismatched semiconductor structures
US7799592B2 (en) * 2006-09-27 2010-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-gate field-effect transistors formed by aspect ratio trapping
US20080187018A1 (en) * 2006-10-19 2008-08-07 Amberwave Systems Corporation Distributed feedback lasers formed via aspect ratio trapping
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
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US7825328B2 (en) * 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US8329541B2 (en) * 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
DE112008002387B4 (de) 2007-09-07 2022-04-07 Taiwan Semiconductor Manufacturing Co., Ltd. Struktur einer Mehrfachübergangs-Solarzelle, Verfahren zur Bildung einer photonischenVorrichtung, Photovoltaische Mehrfachübergangs-Zelle und Photovoltaische Mehrfachübergangs-Zellenvorrichtung,
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
JP5416212B2 (ja) 2008-09-19 2014-02-12 台湾積體電路製造股▲ふん▼有限公司 エピタキシャル層の成長によるデバイス形成
US20100072515A1 (en) 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
US8138066B2 (en) 2008-10-01 2012-03-20 International Business Machines Corporation Dislocation engineering using a scanned laser
CN102379046B (zh) 2009-04-02 2015-06-17 台湾积体电路制造股份有限公司 从晶体材料的非极性平面形成的器件及其制作方法
CN102449775B (zh) * 2009-06-05 2014-07-02 独立行政法人产业技术综合研究所 半导体基板、光电转换器件、半导体基板的制造方法和光电转换器件的制造方法
TWI562195B (en) 2010-04-27 2016-12-11 Pilegrowth Tech S R L Dislocation and stress management by mask-less processes using substrate patterning and methods for device fabrication
RU2586009C1 (ru) * 2014-12-10 2016-06-10 федеральное государственное бюджетное образовательное учреждение высшего образования Кабардино-Балкарский государственный университет им. Х.М. Бербекова Способ изготовления полупроводниковой структуры

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Also Published As

Publication number Publication date
JP3027473B2 (ja) 2000-04-04
EP0505093A2 (de) 1992-09-23
JPH04318918A (ja) 1992-11-10
EP0505093A3 (en) 1994-06-22
DE69225520T2 (de) 1998-10-01
US5091767A (en) 1992-02-25
EP0505093B1 (de) 1998-05-20

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