DE69230238D1 - Informationsverarbeitungsvorrichtung mit Verzweigungsziel-Befehlspufferspeicher - Google Patents

Informationsverarbeitungsvorrichtung mit Verzweigungsziel-Befehlspufferspeicher

Info

Publication number
DE69230238D1
DE69230238D1 DE69230238T DE69230238T DE69230238D1 DE 69230238 D1 DE69230238 D1 DE 69230238D1 DE 69230238 T DE69230238 T DE 69230238T DE 69230238 T DE69230238 T DE 69230238T DE 69230238 D1 DE69230238 D1 DE 69230238D1
Authority
DE
Germany
Prior art keywords
information processing
processing device
target instruction
branch target
instruction buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69230238T
Other languages
English (en)
Other versions
DE69230238T2 (de
Inventor
Takanori Nakamura
Hiroshi Katsuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69230238D1 publication Critical patent/DE69230238D1/de
Application granted granted Critical
Publication of DE69230238T2 publication Critical patent/DE69230238T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
DE69230238T 1991-07-24 1992-07-24 Informationsverarbeitungsvorrichtung mit Verzweigungsziel-Befehlspufferspeicher Expired - Fee Related DE69230238T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3184245A JP2773471B2 (ja) 1991-07-24 1991-07-24 情報処理装置

Publications (2)

Publication Number Publication Date
DE69230238D1 true DE69230238D1 (de) 1999-12-09
DE69230238T2 DE69230238T2 (de) 2000-09-07

Family

ID=16149929

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69230238T Expired - Fee Related DE69230238T2 (de) 1991-07-24 1992-07-24 Informationsverarbeitungsvorrichtung mit Verzweigungsziel-Befehlspufferspeicher

Country Status (5)

Country Link
US (1) US5386519A (de)
EP (1) EP0525666B1 (de)
JP (1) JP2773471B2 (de)
KR (1) KR950010825B1 (de)
DE (1) DE69230238T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2596712B2 (ja) * 1993-07-01 1997-04-02 インターナショナル・ビジネス・マシーンズ・コーポレイション 近接した分岐命令を含む命令の実行を管理するシステム及び方法
US5550995A (en) * 1994-01-03 1996-08-27 Motorola, Inc. Memory cache with automatic alliased entry invalidation and method of operation
US6020618A (en) * 1994-03-30 2000-02-01 Denso Corporation Semiconductor device in which thin silicon portions are formed by electrochemical stop etching method
US6052801A (en) * 1995-05-10 2000-04-18 Intel Corporation Method and apparatus for providing breakpoints on a selectable address range
US5659679A (en) * 1995-05-30 1997-08-19 Intel Corporation Method and apparatus for providing breakpoints on taken jumps and for providing software profiling in a computer system
US5740413A (en) * 1995-06-19 1998-04-14 Intel Corporation Method and apparatus for providing address breakpoints, branch breakpoints, and single stepping
US5621886A (en) * 1995-06-19 1997-04-15 Intel Corporation Method and apparatus for providing efficient software debugging
US5996071A (en) * 1995-12-15 1999-11-30 Via-Cyrix, Inc. Detecting self-modifying code in a pipelined processor with branch processing by comparing latched store address to subsequent target address
GB9805485D0 (en) * 1998-03-13 1998-05-13 Sgs Thomson Microelectronics Microcomputer
US6957327B1 (en) * 1998-12-31 2005-10-18 Stmicroelectronics, Inc. Block-based branch target buffer
US6446197B1 (en) * 1999-10-01 2002-09-03 Hitachi, Ltd. Two modes for executing branch instructions of different lengths and use of branch control instruction and register set loaded with target instructions
US7032100B1 (en) * 1999-12-17 2006-04-18 Koninklijke Philips Electronics N.V. Simple algorithmic cryptography engine
JP3566680B2 (ja) * 2001-09-11 2004-09-15 富士通株式会社 半導体装置の製造方法
JP3760999B2 (ja) 2004-06-15 2006-03-29 セイコーエプソン株式会社 情報処理装置、マイクロコンピュータ及び電子機器
KR100870859B1 (ko) * 2008-03-26 2008-11-27 이호경 볼트를 이용한 피에이치씨 파일의 연결 구조
GB2535514B (en) 2015-02-19 2021-09-22 Advanced Risc Mach Ltd Processor exception handling

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR633350A (fr) * 1926-04-27 1928-01-27 Charrue raboteuse
JPS549456B2 (de) * 1972-07-05 1979-04-24
DE3241357A1 (de) * 1982-11-09 1984-05-10 Siemens AG, 1000 Berlin und 8000 München Vorrichtung zur mikrobefehls-bereitstellung fuer mindestens zwei unabhaengig arbeitende funktionseinheiten in einem integrierten, mikroprogrammierten elektronischen baustein und verfahren zu ihrem betrieb
JPS6051948A (ja) * 1983-08-31 1985-03-23 Hitachi Ltd 情報処理装置
US4691277A (en) * 1984-10-24 1987-09-01 International Business Machines Corp. Small instruction cache using branch target table to effect instruction prefetch
US5146570A (en) * 1984-10-31 1992-09-08 International Business Machines Corporation System executing branch-with-execute instruction resulting in next successive instruction being execute while specified target instruction is prefetched for following execution
JPS61214039A (ja) * 1985-03-20 1986-09-22 Hitachi Ltd キヤツシユメモリ
JP2534662B2 (ja) * 1986-03-25 1996-09-18 日本電気株式会社 命令キヤツシユ制御方法
KR950006590B1 (ko) * 1986-11-14 1995-06-19 가부시기가이샤 히다찌세이사꾸쇼 캐시 메모리를 갖는 마이크로 프로세서
US4933837A (en) * 1986-12-01 1990-06-12 Advanced Micro Devices, Inc. Methods and apparatus for optimizing instruction processing in computer systems employing a combination of instruction cache and high speed consecutive transfer memories
JPS6421628A (en) * 1987-07-17 1989-01-25 Mitsubishi Electric Corp Arithmetic processing unit
GB8728493D0 (en) * 1987-12-05 1988-01-13 Int Computers Ltd Jump prediction
KR970005453B1 (ko) * 1987-12-25 1997-04-16 가부시기가이샤 히다찌세이사꾸쇼 고속처리에 적합한 데이타 처리장치
US5136696A (en) * 1988-06-27 1992-08-04 Prime Computer, Inc. High-performance pipelined central processor for predicting the occurrence of executing single-cycle instructions and multicycle instructions
US5136697A (en) * 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
US5179673A (en) * 1989-12-18 1993-01-12 Digital Equipment Corporation Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline
JP2531822B2 (ja) * 1990-03-14 1996-09-04 甲府日本電気株式会社 命令先行読出し装置

Also Published As

Publication number Publication date
JPH0527971A (ja) 1993-02-05
KR950010825B1 (ko) 1995-09-23
EP0525666A2 (de) 1993-02-03
US5386519A (en) 1995-01-31
EP0525666B1 (de) 1999-11-03
EP0525666A3 (en) 1993-08-25
DE69230238T2 (de) 2000-09-07
JP2773471B2 (ja) 1998-07-09
KR930002935A (ko) 1993-02-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee