DE69230483T2 - Quadraturbusprotokoll zum Ausführen von Transaktionen in einer Rechneranordnung - Google Patents

Quadraturbusprotokoll zum Ausführen von Transaktionen in einer Rechneranordnung

Info

Publication number
DE69230483T2
DE69230483T2 DE69230483T DE69230483T DE69230483T2 DE 69230483 T2 DE69230483 T2 DE 69230483T2 DE 69230483 T DE69230483 T DE 69230483T DE 69230483 T DE69230483 T DE 69230483T DE 69230483 T2 DE69230483 T2 DE 69230483T2
Authority
DE
Germany
Prior art keywords
bus protocol
computer arrangement
executing transactions
quadrature
quadrature bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69230483T
Other languages
English (en)
Other versions
DE69230483D1 (de
Inventor
Russell C Brockmann
Leith L Johnson
William S Jaffe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE69230483D1 publication Critical patent/DE69230483D1/de
Publication of DE69230483T2 publication Critical patent/DE69230483T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
DE69230483T 1991-04-29 1992-04-06 Quadraturbusprotokoll zum Ausführen von Transaktionen in einer Rechneranordnung Expired - Fee Related DE69230483T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/694,265 US5249297A (en) 1991-04-29 1991-04-29 Methods and apparatus for carrying out transactions in a computer system

Publications (2)

Publication Number Publication Date
DE69230483D1 DE69230483D1 (de) 2000-02-03
DE69230483T2 true DE69230483T2 (de) 2000-05-11

Family

ID=24788104

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69230483T Expired - Fee Related DE69230483T2 (de) 1991-04-29 1992-04-06 Quadraturbusprotokoll zum Ausführen von Transaktionen in einer Rechneranordnung

Country Status (5)

Country Link
US (1) US5249297A (de)
EP (1) EP0512685B1 (de)
JP (1) JPH05274252A (de)
KR (1) KR920020316A (de)
DE (1) DE69230483T2 (de)

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DE9321323U1 (de) * 1992-11-04 1997-04-10 Siemens Ag Anordnung mit mehreren aktiven und passiven Busteilnehmern
JP2826028B2 (ja) * 1993-01-28 1998-11-18 富士通株式会社 分散メモリ型プロセッサシステム
CA2116826C (en) * 1993-03-11 1998-11-24 Timothy J. Sullivan Data processing system using a non-multiplexed, asynchronous address/data bus system
US5581713A (en) * 1994-10-25 1996-12-03 Pyramid Technology Corporation Multiprocessor computer backplane bus in which bus transactions are classified into different classes for arbitration
US5812799A (en) * 1995-06-07 1998-09-22 Microunity Systems Engineering, Inc. Non-blocking load buffer and a multiple-priority memory system for real-time multiprocessing
US5737547A (en) * 1995-06-07 1998-04-07 Microunity Systems Engineering, Inc. System for placing entries of an outstanding processor request into a free pool after the request is accepted by a corresponding peripheral device
US6260126B1 (en) 1998-06-05 2001-07-10 International Busines Machines Corporation Data storage subsystem having apparatus for enabling concurrent housekeeping processing while an input/output data transfer occurs
US6189061B1 (en) * 1999-02-01 2001-02-13 Motorola, Inc. Multi-master bus system performing atomic transactions and method of operating same
US8010751B2 (en) * 2002-04-14 2011-08-30 Bay Microsystems Data forwarding engine
US7386743B2 (en) * 2005-06-09 2008-06-10 International Business Machines Corporation Power-managed server and method for managing power consumption
US7467311B2 (en) * 2005-06-09 2008-12-16 International Business Machines Corporation Distributed system and method for managing power usage among server data processing systems
US7421599B2 (en) * 2005-06-09 2008-09-02 International Business Machines Corporation Power management server and method for managing power consumption
US7664968B2 (en) * 2005-06-09 2010-02-16 International Business Machines Corporation System and method for managing power usage of a data processing system subsystem
US7509506B2 (en) * 2005-06-09 2009-03-24 International Business Machines Corporation Hierarchical system and method for managing power usage among server data processing systems
US8805590B2 (en) * 2009-12-24 2014-08-12 International Business Machines Corporation Fan speed control of rack devices where sum of device airflows is greater than maximum airflow of rack
US10055691B2 (en) 2014-09-08 2018-08-21 Pivotal Software, Inc. Stream processing with dynamic event routing

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3886524A (en) * 1973-10-18 1975-05-27 Texas Instruments Inc Asynchronous communication bus
AU518055B2 (en) * 1977-06-06 1981-09-10 Sits Soc It Telecom Siemens Interface unit between a data processor anda remote unit
US4449183A (en) * 1979-07-09 1984-05-15 Digital Equipment Corporation Arbitration scheme for a multiported shared functional device for use in multiprocessing systems
US4320457A (en) * 1980-02-04 1982-03-16 General Automation, Inc. Communication bus acquisition circuit
US4661905A (en) * 1983-09-22 1987-04-28 Digital Equipment Corporation Bus-control mechanism
JPS61166653A (ja) * 1985-01-19 1986-07-28 Panafacom Ltd アドレス変換エラー処理方法
US5121488A (en) * 1986-06-12 1992-06-09 International Business Machines Corporation Sequence controller of an instruction processing unit for placing said unit in a ready, go, hold, or cancel state
US5012409A (en) * 1988-03-10 1991-04-30 Fletcher Mitchell S Operating system for a multi-tasking operating environment
US5129090A (en) * 1988-05-26 1992-07-07 Ibm Corporation System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration
US5235684A (en) * 1988-06-30 1993-08-10 Wang Laboratories, Inc. System bus having multiplexed command/id and data
US4977494A (en) * 1989-02-17 1990-12-11 Hughes Aircraft Company High speed digital motion controller architecture
US4993023A (en) * 1989-06-09 1991-02-12 Honeywell Inc. Apparatus for providing multiple controller interfaces to a standard digital modem and including multiplexed contention resolution
US5072363A (en) * 1989-12-22 1991-12-10 Harris Corporation Multimode resource arbiter providing round robin arbitration or a modified priority arbitration

Also Published As

Publication number Publication date
JPH05274252A (ja) 1993-10-22
DE69230483D1 (de) 2000-02-03
EP0512685A1 (de) 1992-11-11
KR920020316A (ko) 1992-11-21
US5249297A (en) 1993-09-28
EP0512685B1 (de) 1999-12-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE),

8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE

8339 Ceased/non-payment of the annual fee