DE69231702T2 - Verfahren zur Herstellung von Isolationszonen aus Oxid - Google Patents
Verfahren zur Herstellung von Isolationszonen aus OxidInfo
- Publication number
- DE69231702T2 DE69231702T2 DE69231702T DE69231702T DE69231702T2 DE 69231702 T2 DE69231702 T2 DE 69231702T2 DE 69231702 T DE69231702 T DE 69231702T DE 69231702 T DE69231702 T DE 69231702T DE 69231702 T2 DE69231702 T2 DE 69231702T2
- Authority
- DE
- Germany
- Prior art keywords
- oxide
- production
- isolation zones
- zones
- isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/015—Capping layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/117—Oxidation, selective
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/905—Plural dram cells share common contact or common trench
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/912—Charge transfer device using both electron and hole signal carriers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/914—Polysilicon containing oxygen, nitrogen, or carbon, e.g. sipos
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/738,580 US5192707A (en) | 1991-07-31 | 1991-07-31 | Method of forming isolated regions of oxide |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69231702D1 DE69231702D1 (de) | 2001-04-05 |
DE69231702T2 true DE69231702T2 (de) | 2001-09-13 |
Family
ID=24968593
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69231702T Expired - Fee Related DE69231702T2 (de) | 1991-07-31 | 1992-07-30 | Verfahren zur Herstellung von Isolationszonen aus Oxid |
Country Status (4)
Country | Link |
---|---|
US (2) | US5192707A (de) |
EP (1) | EP0526212B1 (de) |
JP (1) | JP3273636B2 (de) |
DE (1) | DE69231702T2 (de) |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1250233B (it) * | 1991-11-29 | 1995-04-03 | St Microelectronics Srl | Procedimento per la fabbricazione di circuiti integrati in tecnologia mos. |
US5310692A (en) * | 1992-05-29 | 1994-05-10 | Sgs-Thomson Microelectronics, Inc. | Method of forming a MOSFET structure with planar surface |
US5371035A (en) * | 1993-02-01 | 1994-12-06 | Motorola Inc. | Method for forming electrical isolation in an integrated circuit device |
JP2685401B2 (ja) * | 1993-06-16 | 1997-12-03 | 財団法人工業技術研究院 | 酸化ケイ素単離領域の形成方法 |
KR970003893B1 (ko) * | 1993-10-25 | 1997-03-22 | 삼성전자 주식회사 | 반도체 장치의 소자 분리 방법 |
DE4336869C2 (de) * | 1993-10-28 | 2003-05-28 | Gold Star Electronics | Verfahren zum Herstellen eines MOS-Transistors |
US5927992A (en) * | 1993-12-22 | 1999-07-27 | Stmicroelectronics, Inc. | Method of forming a dielectric in an integrated circuit |
US5543343A (en) * | 1993-12-22 | 1996-08-06 | Sgs-Thomson Microelectronics, Inc. | Method fabricating an integrated circuit |
US6034410A (en) * | 1994-01-14 | 2000-03-07 | Stmicroelectronics, Inc. | MOSFET structure with planar surface |
KR960005839A (ko) * | 1994-07-06 | 1996-02-23 | 김주용 | 반도체 소자의 필드 산화막 형성방법 |
US5631189A (en) * | 1994-07-13 | 1997-05-20 | Nippon Telegraph And Telephone Corporation | Method of forming element isolation region |
US5814544A (en) * | 1994-07-14 | 1998-09-29 | Vlsi Technology, Inc. | Forming a MOS transistor with a recessed channel |
JP3304621B2 (ja) * | 1994-07-29 | 2002-07-22 | 三菱電機株式会社 | 半導体装置の製造方法 |
US5643825A (en) * | 1994-12-29 | 1997-07-01 | Advanced Micro Devices, Inc. | Integrated circuit isolation process |
US5604370A (en) * | 1995-07-11 | 1997-02-18 | Advanced Micro Devices, Inc. | Field implant for semiconductor device |
US6313034B1 (en) | 1995-08-03 | 2001-11-06 | Chartered Semiconductor Manufacturing | Method for forming integrated circuit device structures from semiconductor substrate oxidation mask layers |
US5837378A (en) * | 1995-09-12 | 1998-11-17 | Micron Technology, Inc. | Method of reducing stress-induced defects in silicon |
DE19535150A1 (de) * | 1995-09-21 | 1997-03-27 | Mosel Vitelic Inc | Verfahren zur Herstellung eines integrierten Halbleiterkreises |
US5747357A (en) * | 1995-09-27 | 1998-05-05 | Mosel Vitelic, Inc. | Modified poly-buffered isolation |
US5702976A (en) | 1995-10-24 | 1997-12-30 | Micron Technology, Inc. | Shallow trench isolation using low dielectric constant insulator |
KR0171982B1 (ko) * | 1995-12-02 | 1999-03-30 | 김주용 | 반도체 소자의 필드 산화막 형성방법 |
US5972776A (en) * | 1995-12-22 | 1999-10-26 | Stmicroelectronics, Inc. | Method of forming a planar isolation structure in an integrated circuit |
KR0172730B1 (ko) * | 1995-12-30 | 1999-03-30 | 김주용 | 반도체 소자의 아이솔레이션 방법 |
US5658822A (en) * | 1996-03-29 | 1997-08-19 | Vanguard International Semiconductor Corporation | Locos method with double polysilicon/silicon nitride spacer |
US5899727A (en) * | 1996-05-02 | 1999-05-04 | Advanced Micro Devices, Inc. | Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization |
US5834360A (en) * | 1996-07-31 | 1998-11-10 | Stmicroelectronics, Inc. | Method of forming an improved planar isolation structure in an integrated circuit |
US5902128A (en) | 1996-10-17 | 1999-05-11 | Micron Technology, Inc. | Process to improve the flow of oxide during field oxidation by fluorine doping |
US5891788A (en) * | 1996-11-14 | 1999-04-06 | Micron Technology, Inc. | Locus isolation technique using high pressure oxidation (hipox) and protective spacers |
US5821153A (en) * | 1996-12-09 | 1998-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to reduce field oxide loss from etches |
JPH11214384A (ja) * | 1998-01-28 | 1999-08-06 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US6001713A (en) * | 1998-09-16 | 1999-12-14 | Advanced Micro Devices, Inc. | Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device |
US6514885B1 (en) * | 2000-05-03 | 2003-02-04 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing method to reduce process induced stress and crystalline defects |
US20030055863A1 (en) * | 2001-07-24 | 2003-03-20 | Spiegel Michael G. | Method and apparatus for managing system resources in an information handling system |
JP2005332996A (ja) * | 2004-05-20 | 2005-12-02 | Oki Electric Ind Co Ltd | 半導体装置、及びその製造方法 |
CN114429983A (zh) * | 2022-04-01 | 2022-05-03 | 北京芯可鉴科技有限公司 | 高压横向双扩散金属氧化物半导体场效应管及其制作方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5197385A (en) * | 1975-02-21 | 1976-08-26 | Handotaisochino seizohoho | |
JPS5552254A (en) * | 1978-10-11 | 1980-04-16 | Nec Corp | Semiconductor device |
JPS5640269A (en) * | 1979-09-11 | 1981-04-16 | Toshiba Corp | Preparation of semiconductor device |
US4508757A (en) * | 1982-12-20 | 1985-04-02 | International Business Machines Corporation | Method of manufacturing a minimum bird's beak recessed oxide isolation structure |
US4407696A (en) * | 1982-12-27 | 1983-10-04 | Mostek Corporation | Fabrication of isolation oxidation for MOS circuit |
DE3329074A1 (de) * | 1983-08-11 | 1985-02-28 | Siemens AG, 1000 Berlin und 8000 München | Verhinderung der oxidationsmitteldiffusion bei der herstellung von halbleiterschichtanordnungen |
US4580156A (en) * | 1983-12-30 | 1986-04-01 | At&T Bell Laboratories | Structured resistive field shields for low-leakage high voltage devices |
US4516316A (en) * | 1984-03-27 | 1985-05-14 | Advanced Micro Devices, Inc. | Method of making improved twin wells for CMOS devices by controlling spatial separation |
JPS6116575A (ja) * | 1984-07-03 | 1986-01-24 | Ricoh Co Ltd | 半導体メモリ装置の製造方法 |
US4630356A (en) * | 1985-09-19 | 1986-12-23 | International Business Machines Corporation | Method of forming recessed oxide isolation with reduced steepness of the birds' neck |
DE3542166A1 (de) * | 1985-11-29 | 1987-06-04 | Telefunken Electronic Gmbh | Halbleiterbauelement |
US4740481A (en) * | 1986-01-21 | 1988-04-26 | Motorola Inc. | Method of preventing hillock formation in polysilicon layer by oxygen implanation |
US5028559A (en) * | 1989-03-23 | 1991-07-02 | Motorola Inc. | Fabrication of devices having laterally isolated semiconductor regions |
US5002898A (en) * | 1989-10-19 | 1991-03-26 | At&T Bell Laboratories | Integrated-circuit device isolation |
US5159430A (en) * | 1991-07-24 | 1992-10-27 | Micron Technology, Inc. | Vertically integrated oxygen-implanted polysilicon resistor |
-
1991
- 1991-07-31 US US07/738,580 patent/US5192707A/en not_active Expired - Lifetime
-
1992
- 1992-07-30 EP EP92306967A patent/EP0526212B1/de not_active Expired - Lifetime
- 1992-07-30 DE DE69231702T patent/DE69231702T2/de not_active Expired - Fee Related
- 1992-07-31 JP JP20470292A patent/JP3273636B2/ja not_active Expired - Lifetime
- 1992-09-04 US US07/940,451 patent/US5338968A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5338968A (en) | 1994-08-16 |
EP0526212A3 (de) | 1995-10-04 |
EP0526212A2 (de) | 1993-02-03 |
US5192707A (en) | 1993-03-09 |
DE69231702D1 (de) | 2001-04-05 |
EP0526212B1 (de) | 2001-02-28 |
JPH05206115A (ja) | 1993-08-13 |
JP3273636B2 (ja) | 2002-04-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |