DE69231803D1 - Verfahren zur Herstellung einer Halbleiteranordnung - Google Patents
Verfahren zur Herstellung einer HalbleiteranordnungInfo
- Publication number
- DE69231803D1 DE69231803D1 DE69231803T DE69231803T DE69231803D1 DE 69231803 D1 DE69231803 D1 DE 69231803D1 DE 69231803 T DE69231803 T DE 69231803T DE 69231803 T DE69231803 T DE 69231803T DE 69231803 D1 DE69231803 D1 DE 69231803D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76275—Vertical isolation by bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76281—Lateral isolation by selective oxidation of silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/05—Etch and refill
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/135—Removal of substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26504791A JP2858383B2 (ja) | 1991-10-14 | 1991-10-14 | 半導体装置の製造方法 |
JP3265057A JP3021850B2 (ja) | 1991-10-14 | 1991-10-14 | 半導体装置の製造方法 |
JP3265046A JP2812013B2 (ja) | 1991-10-14 | 1991-10-14 | 半導体装置の製造方法 |
PCT/JP1992/001326 WO1993008596A1 (en) | 1991-10-14 | 1992-10-12 | Method for fabrication of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69231803D1 true DE69231803D1 (de) | 2001-05-31 |
DE69231803T2 DE69231803T2 (de) | 2001-12-06 |
Family
ID=27335347
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69231803T Expired - Lifetime DE69231803T2 (de) | 1991-10-14 | 1992-10-12 | Verfahren zur Herstellung einer Halbleiteranordnung |
Country Status (4)
Country | Link |
---|---|
US (1) | US5480832A (de) |
EP (1) | EP0562127B1 (de) |
DE (1) | DE69231803T2 (de) |
WO (1) | WO1993008596A1 (de) |
Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07505013A (ja) * | 1991-11-15 | 1995-06-01 | アナログ・デバイセズ・インコーポレイテッド | 絶縁体を充填した深いトレンチを半導体基板に製作する方法 |
KR0162510B1 (ko) * | 1993-07-12 | 1999-02-01 | 가네꼬 히사시 | 반도체 장치 및 그 제조방법 |
JP2773611B2 (ja) * | 1993-11-17 | 1998-07-09 | 株式会社デンソー | 絶縁物分離半導体装置 |
JP3033412B2 (ja) * | 1993-11-26 | 2000-04-17 | 株式会社デンソー | 半導体装置の製造方法 |
DE4341171C2 (de) * | 1993-12-02 | 1997-04-17 | Siemens Ag | Verfahren zur Herstellung einer integrierten Schaltungsanordnung |
US5753529A (en) * | 1994-05-05 | 1998-05-19 | Siliconix Incorporated | Surface mount and flip chip technology for total integrated circuit isolation |
JPH07326659A (ja) * | 1994-06-02 | 1995-12-12 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
US5691248A (en) * | 1995-07-26 | 1997-11-25 | International Business Machines Corporation | Methods for precise definition of integrated circuit chip edges |
KR0161432B1 (ko) * | 1995-09-13 | 1999-02-01 | 김광호 | 소자분리 영역의 면적을 감소시키기 위한 트랜지스터 제조방법 |
TW309647B (de) * | 1995-12-30 | 1997-07-01 | Hyundai Electronics Ind | |
KR970052023A (ko) * | 1995-12-30 | 1997-07-29 | 김주용 | 에스 오 아이 소자 및 그의 제조방법 |
US5683945A (en) * | 1996-05-16 | 1997-11-04 | Siemens Aktiengesellschaft | Uniform trench fill recess by means of isotropic etching |
US6291315B1 (en) * | 1996-07-11 | 2001-09-18 | Denso Corporation | Method for etching trench in manufacturing semiconductor devices |
US5811315A (en) * | 1997-03-13 | 1998-09-22 | National Semiconductor Corporation | Method of forming and planarizing deep isolation trenches in a silicon-on-insulator (SOI) structure |
US6013558A (en) * | 1997-08-06 | 2000-01-11 | Vlsi Technology, Inc. | Silicon-enriched shallow trench oxide for reduced recess during LDD spacer etch |
US6333274B2 (en) * | 1998-03-31 | 2001-12-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device including a seamless shallow trench isolation step |
US5880006A (en) * | 1998-05-22 | 1999-03-09 | Vlsi Technology, Inc. | Method for fabrication of a semiconductor device |
KR100318467B1 (ko) * | 1998-06-30 | 2002-02-19 | 박종섭 | 본딩형실리콘이중막웨이퍼제조방법 |
KR20000015663A (ko) | 1998-08-31 | 2000-03-15 | 김영환 | 반도체 소자의 격리막 형성방법 |
US6353246B1 (en) | 1998-11-23 | 2002-03-05 | International Business Machines Corporation | Semiconductor device including dislocation in merged SOI/DRAM chips |
JP3546789B2 (ja) | 1999-12-24 | 2004-07-28 | 株式会社デンソー | 半導体装置の製造方法 |
FR2807568A1 (fr) * | 2000-04-10 | 2001-10-12 | St Microelectronics Sa | Procede de formation de couches enterrees |
US6486043B1 (en) | 2000-08-31 | 2002-11-26 | International Business Machines Corporation | Method of forming dislocation filter in merged SOI and non-SOI chips |
US6797591B1 (en) * | 2000-09-14 | 2004-09-28 | Analog Devices, Inc. | Method for forming a semiconductor device and a semiconductor device formed by the method |
EP1220312A1 (de) * | 2000-12-29 | 2002-07-03 | STMicroelectronics S.r.l. | Verfahren zur Integration eines Halbleiterbauelements auf einem SOI Substrat mit mindestens einer dielektrisch isolierten Wanne |
GB2372631B (en) * | 2001-02-22 | 2005-08-03 | Mitel Semiconductor Ltd | Semiconductor-on-insulator structure |
JP4852792B2 (ja) * | 2001-03-30 | 2012-01-11 | 株式会社デンソー | 半導体装置の製造方法 |
JP2003017704A (ja) | 2001-06-29 | 2003-01-17 | Denso Corp | 半導体装置 |
JP4157718B2 (ja) * | 2002-04-22 | 2008-10-01 | キヤノンアネルバ株式会社 | 窒化シリコン膜作製方法及び窒化シリコン膜作製装置 |
US7358164B2 (en) * | 2005-06-16 | 2008-04-15 | International Business Machines Corporation | Crystal imprinting methods for fabricating substrates with thin active silicon layers |
US7488647B1 (en) | 2005-08-11 | 2009-02-10 | National Semiconductor Corporation | System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device |
US7399686B2 (en) * | 2005-09-01 | 2008-07-15 | International Business Machines Corporation | Method and apparatus for making coplanar dielectrically-isolated regions of different semiconductor materials on a substrate |
JP2007317954A (ja) * | 2006-05-26 | 2007-12-06 | Nec Electronics Corp | 半導体装置及びその製造方法 |
US20100117188A1 (en) * | 2007-03-05 | 2010-05-13 | General Electric Company | Method for producing trench isolation in silicon carbide and gallium nitride and articles made thereby |
US7750406B2 (en) * | 2007-04-20 | 2010-07-06 | International Business Machines Corporation | Design structure incorporating a hybrid substrate |
US7651902B2 (en) * | 2007-04-20 | 2010-01-26 | International Business Machines Corporation | Hybrid substrates and methods for forming such hybrid substrates |
US8049297B2 (en) * | 2007-12-11 | 2011-11-01 | Hvvi Semiconductors, Inc. | Semiconductor structure |
US7893485B2 (en) * | 2007-12-13 | 2011-02-22 | International Business Machines Corporation | Vertical SOI trench SONOS cell |
KR101096907B1 (ko) * | 2009-10-05 | 2011-12-22 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 형성방법 |
US10707330B2 (en) * | 2018-02-15 | 2020-07-07 | Globalfoundries Inc. | Semiconductor device with interconnect to source/drain |
CN113314822B (zh) * | 2021-05-31 | 2022-03-22 | 成都海威华芯科技有限公司 | 一种mems滤波器器件背孔的制作工艺和mems滤波器 |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3966577A (en) * | 1973-08-27 | 1976-06-29 | Trw Inc. | Dielectrically isolated semiconductor devices |
US4307180A (en) * | 1980-08-22 | 1981-12-22 | International Business Machines Corp. | Process of forming recessed dielectric regions in a monocrystalline silicon substrate |
US4389294A (en) * | 1981-06-30 | 1983-06-21 | International Business Machines Corporation | Method for avoiding residue on a vertical walled mesa |
JPS58190040A (ja) * | 1982-04-30 | 1983-11-05 | Nec Corp | 半導体装置の製造方法 |
JPS59208744A (ja) * | 1983-05-13 | 1984-11-27 | Hitachi Ltd | 半導体装置 |
JPS615544A (ja) * | 1984-06-19 | 1986-01-11 | Toshiba Corp | 半導体装置の製造方法 |
JPS618945A (ja) * | 1984-06-25 | 1986-01-16 | Nec Corp | 半導体集積回路装置 |
JPS6159852A (ja) * | 1984-08-31 | 1986-03-27 | Toshiba Corp | 半導体装置の製造方法 |
US4571819A (en) * | 1984-11-01 | 1986-02-25 | Ncr Corporation | Method for forming trench isolation structures |
JPS61214446A (ja) * | 1985-03-19 | 1986-09-24 | Toshiba Corp | 半導体装置の製造方法 |
US4671851A (en) * | 1985-10-28 | 1987-06-09 | International Business Machines Corporation | Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique |
JPS62214638A (ja) * | 1986-03-17 | 1987-09-21 | Fujitsu Ltd | 半導体装置の製造方法 |
US4897154A (en) * | 1986-07-03 | 1990-01-30 | International Business Machines Corporation | Post dry-etch cleaning method for restoring wafer properties |
JPS6333839A (ja) * | 1986-07-28 | 1988-02-13 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JPS6386560A (ja) * | 1986-09-30 | 1988-04-16 | Toshiba Corp | 半導体装置の製造方法 |
JP2788269B2 (ja) * | 1988-02-08 | 1998-08-20 | 株式会社東芝 | 半導体装置およびその製造方法 |
JPH01265536A (ja) * | 1988-04-15 | 1989-10-23 | Citizen Watch Co Ltd | 半導体集積回路における素子分離領域の形成方法 |
JPH0267963A (ja) * | 1988-09-01 | 1990-03-07 | Kaken:Kk | 自動微量成分測定方法及びその装置 |
JPH02148855A (ja) * | 1988-11-30 | 1990-06-07 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US5028559A (en) * | 1989-03-23 | 1991-07-02 | Motorola Inc. | Fabrication of devices having laterally isolated semiconductor regions |
US4952524A (en) * | 1989-05-05 | 1990-08-28 | At&T Bell Laboratories | Semiconductor device manufacture including trench formation |
EP0398468A3 (de) * | 1989-05-16 | 1991-03-13 | Kabushiki Kaisha Toshiba | Dielektrisch isoliertes Substrat und Halbleiteranordnung mit diesem Substrat |
JPH03155650A (ja) * | 1989-08-10 | 1991-07-03 | Oki Electric Ind Co Ltd | 半導体集積回路装置の製造方法 |
JPH0821619B2 (ja) * | 1989-10-13 | 1996-03-04 | 株式会社東芝 | 半導体装置 |
JPH03129854A (ja) * | 1989-10-16 | 1991-06-03 | Toshiba Corp | 半導体装置の製造方法 |
JPH03149836A (ja) * | 1989-11-07 | 1991-06-26 | Fuji Electric Co Ltd | 張り合わせ基板を用いた半導体装置の製造方法 |
JP2820465B2 (ja) * | 1989-11-07 | 1998-11-05 | 富士通株式会社 | 半導体装置の製造方法 |
JP2777920B2 (ja) * | 1989-12-20 | 1998-07-23 | 富士通株式会社 | 半導体装置及びその製造方法 |
JPH04209551A (ja) * | 1990-12-06 | 1992-07-30 | Fujitsu Ltd | 半導体装置の製造方法 |
-
1992
- 1992-10-12 EP EP93908767A patent/EP0562127B1/de not_active Expired - Lifetime
- 1992-10-12 US US08/075,514 patent/US5480832A/en not_active Expired - Lifetime
- 1992-10-12 WO PCT/JP1992/001326 patent/WO1993008596A1/ja active IP Right Grant
- 1992-10-12 DE DE69231803T patent/DE69231803T2/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5480832A (en) | 1996-01-02 |
DE69231803T2 (de) | 2001-12-06 |
EP0562127A1 (de) | 1993-09-29 |
EP0562127A4 (en) | 1994-11-23 |
WO1993008596A1 (en) | 1993-04-29 |
EP0562127B1 (de) | 2001-04-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
R071 | Expiry of right |
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