DE69300523T2 - Prozessorschnittstellenschaltung zum Austausch von seriellen digitalen Daten mit einem Peripheriegerät. - Google Patents

Prozessorschnittstellenschaltung zum Austausch von seriellen digitalen Daten mit einem Peripheriegerät.

Info

Publication number
DE69300523T2
DE69300523T2 DE69300523T DE69300523T DE69300523T2 DE 69300523 T2 DE69300523 T2 DE 69300523T2 DE 69300523 T DE69300523 T DE 69300523T DE 69300523 T DE69300523 T DE 69300523T DE 69300523 T2 DE69300523 T2 DE 69300523T2
Authority
DE
Germany
Prior art keywords
digital data
peripheral device
interface circuit
processor interface
serial digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69300523T
Other languages
English (en)
Other versions
DE69300523D1 (de
Inventor
Jean-Claude Michalina
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Priority claimed from EP93402872A external-priority patent/EP0655691B1/de
Application granted granted Critical
Publication of DE69300523D1 publication Critical patent/DE69300523D1/de
Publication of DE69300523T2 publication Critical patent/DE69300523T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration
    • G06F13/4036—Coupling between buses using bus bridges with arbitration and deadlock prevention
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
DE69300523T 1993-11-26 1993-11-26 Prozessorschnittstellenschaltung zum Austausch von seriellen digitalen Daten mit einem Peripheriegerät. Expired - Fee Related DE69300523T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP93402872A EP0655691B1 (de) 1992-07-29 1993-11-26 Prozessorschnittstellenschaltung zum Austausch von seriellen digitalen Daten mit einem Peripheriegerät

Publications (2)

Publication Number Publication Date
DE69300523D1 DE69300523D1 (de) 1995-10-26
DE69300523T2 true DE69300523T2 (de) 1996-03-14

Family

ID=8214773

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69300523T Expired - Fee Related DE69300523T2 (de) 1993-11-26 1993-11-26 Prozessorschnittstellenschaltung zum Austausch von seriellen digitalen Daten mit einem Peripheriegerät.

Country Status (3)

Country Link
US (1) US5717948A (de)
JP (1) JPH0816513A (de)
DE (1) DE69300523T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10254827A (ja) * 1997-03-06 1998-09-25 Canon Inc 拡張カードおよび拡張カードのアクセス制御方法およびコンピュータが読み出し可能なプログラムを格納した記憶媒体
US6185641B1 (en) * 1997-05-01 2001-02-06 Standard Microsystems Corp. Dynamically allocating space in RAM shared between multiple USB endpoints and USB host
US6112266A (en) * 1998-01-22 2000-08-29 Pc-Tel, Inc. Host signal processing modem using a software circular buffer in system memory and direct transfers of samples to maintain a communication signal
US6038626A (en) * 1998-03-17 2000-03-14 International Business Machines Corporation Method for controlling data transfers and routing
US5996040A (en) * 1998-03-17 1999-11-30 International Business Machines Corporation Scalable, modular selector system
US6256687B1 (en) * 1998-08-04 2001-07-03 Intel Corporation Managing data flow between a serial bus device and a parallel port
US6119195A (en) * 1998-08-04 2000-09-12 Intel Corporation Virtualizing serial bus information point by address mapping via a parallel port
US6651184B1 (en) * 1999-11-03 2003-11-18 Hewlett-Packard Development Company, L.P. Isochronous transfer mode on a universal serial bus with error correction algorithms
US7308633B2 (en) * 2004-11-30 2007-12-11 Lsi Corporation Master controller architecture
US7778674B2 (en) * 2004-12-29 2010-08-17 St-Ericsson Sa Communication apparatus having a SIM interface compatible with radio isolation
KR100685003B1 (ko) * 2005-05-28 2007-02-20 삼성전자주식회사 인터페이스장치, 영상처리장치 및 데이터통신방법
WO2013180724A1 (en) * 2012-05-31 2013-12-05 Intel Corporation Data interface synchronization
US10318420B2 (en) * 2014-10-31 2019-06-11 Hewlett Packard Enterprise Development Lp Draining a write queue based on information from a read queue
US10534540B2 (en) 2016-06-06 2020-01-14 Micron Technology, Inc. Memory protocol
CN117667777A (zh) * 2022-08-30 2024-03-08 深圳市中兴微电子技术有限公司 存储器访问控制电路及存储器访问控制方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1228677A (en) * 1984-06-21 1987-10-27 Cray Research, Inc. Peripheral interface system
DE3678092D1 (de) * 1985-09-30 1991-04-18 Siemens Ag Verfahren zur bit- und bytesynchronen datenuebertragung ueber eine serielle schnittstelle.
US5228129A (en) * 1987-04-01 1993-07-13 Digital Equipment Corporation Synchronous communication interface for reducing the effect of data processor latency
US5163132A (en) * 1987-09-24 1992-11-10 Ncr Corporation Integrated controller using alternately filled and emptied buffers for controlling bi-directional data transfer between a processor and a data storage device
US4887076A (en) * 1987-10-16 1989-12-12 Digital Equipment Corporation Computer interconnect coupler for clusters of data processing devices
US5208913A (en) * 1988-06-22 1993-05-04 Sharp Kabushiki Kaisha Buffer memory for synchronizing data transmission and reception between two devices having mutually different operating speeds and operating methods therefor
FR2636448B1 (fr) * 1988-09-15 1994-07-22 Finger Ulrich Dispositif d'acquisition de donnees pour processeur
US5124980A (en) * 1989-03-20 1992-06-23 Maki Gerald G Synchronous multiport digital 2-way communications network using T1 PCM on a CATV cable
US5448701A (en) * 1992-12-22 1995-09-05 International Business Machines Corporation Flow controller for shared bus used by plural resources

Also Published As

Publication number Publication date
JPH0816513A (ja) 1996-01-19
DE69300523D1 (de) 1995-10-26
US5717948A (en) 1998-02-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee