DE69304404D1 - Verfahren und Vorrichtung zur Programmierung von zellulären programmierbaren integrierten Schaltungen - Google Patents
Verfahren und Vorrichtung zur Programmierung von zellulären programmierbaren integrierten SchaltungenInfo
- Publication number
- DE69304404D1 DE69304404D1 DE69304404T DE69304404T DE69304404D1 DE 69304404 D1 DE69304404 D1 DE 69304404D1 DE 69304404 T DE69304404 T DE 69304404T DE 69304404 T DE69304404 T DE 69304404T DE 69304404 D1 DE69304404 D1 DE 69304404D1
- Authority
- DE
- Germany
- Prior art keywords
- series
- programmable
- switches
- elements
- integrated circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318516—Test of programmable logic devices [PLDs]
- G01R31/318519—Test of field programmable gate arrays [FPGA]
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/880,908 US5237219A (en) | 1992-05-08 | 1992-05-08 | Methods and apparatus for programming cellular programmable logic integrated circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69304404D1 true DE69304404D1 (de) | 1996-10-10 |
Family
ID=25377376
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69304404T Expired - Lifetime DE69304404D1 (de) | 1992-05-08 | 1993-04-07 | Verfahren und Vorrichtung zur Programmierung von zellulären programmierbaren integrierten Schaltungen |
Country Status (4)
Country | Link |
---|---|
US (1) | US5237219A (de) |
EP (1) | EP0569136B1 (de) |
JP (1) | JP3247196B2 (de) |
DE (1) | DE69304404D1 (de) |
Families Citing this family (55)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5367208A (en) | 1986-09-19 | 1994-11-22 | Actel Corporation | Reconfigurable programmable interconnect architecture |
JPH01213115A (ja) * | 1988-02-09 | 1989-08-25 | Taiyo Fishery Co Ltd | レトルト用罐詰容器の真空シール方法及び装置 |
US5528600A (en) | 1991-01-28 | 1996-06-18 | Actel Corporation | Testability circuits for logic arrays |
DE4139153C2 (de) * | 1991-11-28 | 1995-01-19 | Siemens Ag | Verfahren zum Programmieren von programmierbaren integrierten Schaltkreisen |
JP2909328B2 (ja) * | 1992-11-02 | 1999-06-23 | 株式会社東芝 | フィールドプログラマブルゲートアレイ |
US5550843A (en) * | 1994-04-01 | 1996-08-27 | Xilinx, Inc. | Programmable scan chain testing structure and method |
US5796750A (en) * | 1994-04-22 | 1998-08-18 | Lattice Semiconductor Corporation | Method for programming a programmable logic device in an automatic tester |
US5802540A (en) * | 1995-11-08 | 1998-09-01 | Altera Corporation | Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices |
US5424655A (en) * | 1994-05-20 | 1995-06-13 | Quicklogic Corporation | Programmable application specific integrated circuit employing antifuses and methods therefor |
US5442306A (en) * | 1994-09-09 | 1995-08-15 | At&T Corp. | Field programmable gate array using look-up tables, multiplexers and decoders |
US5548228A (en) * | 1994-09-28 | 1996-08-20 | Altera Corporation | Reconfigurable programmable logic device having static and non-volatile memory |
US5737612A (en) * | 1994-09-30 | 1998-04-07 | Cypress Semiconductor Corp. | Power-on reset control circuit |
JP2961126B2 (ja) * | 1995-02-13 | 1999-10-12 | セントラル硝子株式会社 | 三次元光メモリーガラス素子からなる記録媒体及びその記録方法 |
GB9508931D0 (en) | 1995-05-02 | 1995-06-21 | Xilinx Inc | Programmable switch for FPGA input/output signals |
US5543730A (en) | 1995-05-17 | 1996-08-06 | Altera Corporation | Techniques for programming programmable logic array devices |
US5867422A (en) * | 1995-08-08 | 1999-02-02 | University Of South Florida | Computer memory chip with field programmable memory cell arrays (fpmcas), and method of configuring |
US5741720A (en) * | 1995-10-04 | 1998-04-21 | Actel Corporation | Method of programming an improved metal-to-metal via-type antifuse |
US5592102A (en) * | 1995-10-19 | 1997-01-07 | Altera Corporation | Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices |
US5555214A (en) | 1995-11-08 | 1996-09-10 | Altera Corporation | Apparatus for serial reading and writing of random access memory arrays |
US5751163A (en) * | 1996-04-16 | 1998-05-12 | Lattice Semiconductor Corporation | Parallel programming of in-system (ISP) programmable devices using an automatic tester |
US6384630B2 (en) | 1996-06-05 | 2002-05-07 | Altera Corporation | Techniques for programming programmable logic array devices |
US5859562A (en) * | 1996-12-24 | 1999-01-12 | Actel Corporation | Programming circuit for antifuses using bipolar and SCR devices |
US6091258A (en) * | 1997-02-05 | 2000-07-18 | Altera Corporation | Redundancy circuitry for logic circuits |
US6034536A (en) * | 1997-02-05 | 2000-03-07 | Altera Corporation | Redundancy circuitry for logic circuits |
US5910732A (en) * | 1997-03-12 | 1999-06-08 | Xilinx, Inc. | Programmable gate array having shared signal lines for interconnect and configuration |
US5995419A (en) * | 1998-06-25 | 1999-11-30 | Xilinx, Inc. | Repairable memory cell for a memory cell array |
US5831907A (en) * | 1997-05-19 | 1998-11-03 | Xilinx, Inc. | Repairable memory cell for a memory cell array |
EP0983549B1 (de) | 1997-05-23 | 2001-12-12 | Altera Corporation (a Delaware Corporation) | Redundanzschaltung für programmierbare logikanordnung mit verschachtelten eingangsschaltkreisen |
US6128215A (en) * | 1997-08-19 | 2000-10-03 | Altera Corporation | Static random access memory circuits |
US6072332A (en) * | 1997-10-14 | 2000-06-06 | Altera Corporation | Variable depth memories for programmable logic devices |
US6157210A (en) | 1997-10-16 | 2000-12-05 | Altera Corporation | Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits |
US6011406A (en) * | 1997-10-28 | 2000-01-04 | Altera Corporation | Ultra-fast configuration mode for a programmable logic device |
US5940345A (en) * | 1997-12-12 | 1999-08-17 | Cypress Semiconductor Corp. | Combinational logic feedback circuit to ensure correct power-on-reset of a four-bit synchronous shift register |
US6172520B1 (en) | 1997-12-30 | 2001-01-09 | Xilinx, Inc. | FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA |
US6028445A (en) * | 1997-12-30 | 2000-02-22 | Xilinx, Inc. | Decoder structure and method for FPGA configuration |
US6201404B1 (en) | 1998-07-14 | 2001-03-13 | Altera Corporation | Programmable logic device with redundant circuitry |
US6301695B1 (en) | 1999-01-14 | 2001-10-09 | Xilinx, Inc. | Methods to securely configure an FPGA using macro markers |
US6305005B1 (en) | 1999-01-14 | 2001-10-16 | Xilinx, Inc. | Methods to securely configure an FPGA using encrypted macros |
US6160418A (en) * | 1999-01-14 | 2000-12-12 | Xilinx, Inc. | Integrated circuit with selectively disabled logic blocks |
US6357037B1 (en) | 1999-01-14 | 2002-03-12 | Xilinx, Inc. | Methods to securely configure an FPGA to accept selected macros |
US6324676B1 (en) | 1999-01-14 | 2001-11-27 | Xilinx, Inc. | FPGA customizable to accept selected macros |
US6654889B1 (en) | 1999-02-19 | 2003-11-25 | Xilinx, Inc. | Method and apparatus for protecting proprietary configuration data for programmable logic devices |
US6407576B1 (en) * | 1999-03-04 | 2002-06-18 | Altera Corporation | Interconnection and input/output resources for programmable logic integrated circuit devices |
WO2003032159A2 (en) * | 2001-10-11 | 2003-04-17 | Altera Corporation | Error detection on programmable logic resources |
US7162644B1 (en) | 2002-03-29 | 2007-01-09 | Xilinx, Inc. | Methods and circuits for protecting proprietary configuration data for programmable logic devices |
US6996713B1 (en) | 2002-03-29 | 2006-02-07 | Xilinx, Inc. | Method and apparatus for protecting proprietary decryption keys for programmable logic devices |
US6842039B1 (en) | 2002-10-21 | 2005-01-11 | Altera Corporation | Configuration shift register |
US7111110B1 (en) | 2002-12-10 | 2006-09-19 | Altera Corporation | Versatile RAM for programmable logic device |
US8085857B1 (en) | 2003-09-25 | 2011-12-27 | Cypress Semiconductor Corporation | Digital-compatible multi-state-sense input |
US7343470B1 (en) | 2003-09-26 | 2008-03-11 | Altera Corporation | Techniques for sequentially transferring data from a memory device through a parallel interface |
US7328377B1 (en) | 2004-01-27 | 2008-02-05 | Altera Corporation | Error correction for programmable logic integrated circuits |
US6972987B1 (en) | 2004-05-27 | 2005-12-06 | Altera Corporation | Techniques for reducing power consumption in memory cells |
US7379325B1 (en) * | 2005-12-16 | 2008-05-27 | Maxim Intergrated Products, Inc. | Non-imprinting memory with high speed erase |
US7755419B2 (en) | 2006-01-17 | 2010-07-13 | Cypress Semiconductor Corporation | Low power beta multiplier start-up circuit and method |
US7830200B2 (en) * | 2006-01-17 | 2010-11-09 | Cypress Semiconductor Corporation | High voltage tolerant bias circuit with low voltage transistors |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4864544A (en) * | 1986-03-12 | 1989-09-05 | Advanced Micro Devices, Inc. | A Ram cell having means for controlling a bidirectional shift |
US5059819A (en) * | 1986-12-26 | 1991-10-22 | Hitachi, Ltd. | Integrated logic circuit |
US4805139A (en) * | 1987-10-22 | 1989-02-14 | Advanced Micro Devices, Inc. | Propagating FIFO storage device |
JP2837682B2 (ja) * | 1989-01-13 | 1998-12-16 | 株式会社日立製作所 | 半導体記憶装置 |
US5021689A (en) * | 1989-01-19 | 1991-06-04 | National Semiconductor Corp. | Multiple page programmable logic architecture |
US5255203A (en) * | 1989-08-15 | 1993-10-19 | Advanced Micro Devices, Inc. | Interconnect structure for programmable logic device |
US5095462A (en) * | 1990-05-25 | 1992-03-10 | Advanced Micro Devices, Inc. | Fifo information storage apparatus including status and logic modules for each cell |
-
1992
- 1992-05-08 US US07/880,908 patent/US5237219A/en not_active Expired - Lifetime
-
1993
- 1993-04-07 DE DE69304404T patent/DE69304404D1/de not_active Expired - Lifetime
- 1993-04-07 EP EP93302744A patent/EP0569136B1/de not_active Expired - Lifetime
- 1993-05-07 JP JP10703193A patent/JP3247196B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0677814A (ja) | 1994-03-18 |
US5237219A (en) | 1993-08-17 |
EP0569136A3 (de) | 1994-02-16 |
JP3247196B2 (ja) | 2002-01-15 |
EP0569136B1 (de) | 1996-09-04 |
EP0569136A2 (de) | 1993-11-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de |