DE69317012D1 - Herstellungsverfahren einer Verbindungsstruktur in einer integrierten Schaltung - Google Patents

Herstellungsverfahren einer Verbindungsstruktur in einer integrierten Schaltung

Info

Publication number
DE69317012D1
DE69317012D1 DE69317012T DE69317012T DE69317012D1 DE 69317012 D1 DE69317012 D1 DE 69317012D1 DE 69317012 T DE69317012 T DE 69317012T DE 69317012 T DE69317012 T DE 69317012T DE 69317012 D1 DE69317012 D1 DE 69317012D1
Authority
DE
Germany
Prior art keywords
manufacturing
integrated circuit
connection structure
connection
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69317012T
Other languages
English (en)
Other versions
DE69317012T2 (de
Inventor
Che-Chia Wei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Publication of DE69317012D1 publication Critical patent/DE69317012D1/de
Application granted granted Critical
Publication of DE69317012T2 publication Critical patent/DE69317012T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
DE69317012T 1992-05-29 1993-05-25 Herstellungsverfahren einer Verbindungsstruktur in einer integrierten Schaltung Expired - Fee Related DE69317012T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/891,450 US5313084A (en) 1992-05-29 1992-05-29 Interconnect structure for an integrated circuit

Publications (2)

Publication Number Publication Date
DE69317012D1 true DE69317012D1 (de) 1998-03-26
DE69317012T2 DE69317012T2 (de) 1998-06-04

Family

ID=25398212

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69317012T Expired - Fee Related DE69317012T2 (de) 1992-05-29 1993-05-25 Herstellungsverfahren einer Verbindungsstruktur in einer integrierten Schaltung

Country Status (4)

Country Link
US (2) US5313084A (de)
EP (1) EP0572214B1 (de)
JP (1) JPH06177132A (de)
DE (1) DE69317012T2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950009283B1 (ko) * 1992-08-24 1995-08-18 삼성전자주식회사 반도체장치의 제조방법
KR0140464B1 (ko) * 1993-08-26 1998-07-15 세끼자와 다다시 실리사이드 전극을 갖는 반도체장치의 제조방법
JP2677168B2 (ja) * 1993-09-17 1997-11-17 日本電気株式会社 半導体装置の製造方法
JP3334370B2 (ja) * 1994-10-13 2002-10-15 ヤマハ株式会社 半導体デバイス
JPH08130244A (ja) * 1994-11-02 1996-05-21 Mitsubishi Electric Corp 局所配線の形成方法
JP2630290B2 (ja) * 1995-01-30 1997-07-16 日本電気株式会社 半導体装置の製造方法
US5536683A (en) * 1995-06-15 1996-07-16 United Microelectronics Corporation Method for interconnecting semiconductor devices
US5554549A (en) * 1995-07-03 1996-09-10 Taiwan Semiconductor Manufacturing Company Ltd. Salicide process for FETs
JPH10135238A (ja) * 1996-11-05 1998-05-22 Sony Corp 半導体装置およびその製造方法
US5830775A (en) * 1996-11-26 1998-11-03 Sharp Microelectronics Technology, Inc. Raised silicided source/drain electrode formation with reduced substrate silicon consumption
JPH10189483A (ja) * 1996-12-26 1998-07-21 Fujitsu Ltd 半導体装置の製造方法及び半導体装置
JP3119190B2 (ja) * 1997-01-24 2000-12-18 日本電気株式会社 半導体装置の製造方法
US6004869A (en) * 1997-04-25 1999-12-21 Micron Technology, Inc. Method for making a low resistivity electrode having a near noble metal
KR19990012160A (ko) * 1997-07-28 1999-02-25 윤종용 소스/드레인 실리사이드를 갖는 모스 소자 및 그 제조 방법
US6096639A (en) * 1998-04-07 2000-08-01 Advanced Micro Devices, Inc. Method of forming a local interconnect by conductive layer patterning
EP1306898A1 (de) * 2001-10-29 2003-05-02 Dialog Semiconductor GmbH Sub-Milliohm-Zwischenverbindung auf einem Chip
US9006071B2 (en) 2013-03-27 2015-04-14 International Business Machines Corporation Thin channel MOSFET with silicide local interconnect

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5121186A (en) * 1984-06-15 1992-06-09 Hewlett-Packard Company Integrated circuit device having improved junction connections
US4751198A (en) * 1985-09-11 1988-06-14 Texas Instruments Incorporated Process for making contacts and interconnections using direct-reacted silicide
US4690730A (en) * 1986-03-07 1987-09-01 Texas Instruments Incorporated Oxide-capped titanium silicide formation
US4822749A (en) * 1987-08-27 1989-04-18 North American Philips Corporation, Signetics Division Self-aligned metallization for semiconductor device and process using selectively deposited tungsten
KR910005401B1 (ko) * 1988-09-07 1991-07-29 경상현 비결정 실리콘을 이용한 자기정렬 트랜지스터 제조방법
JPH02199838A (ja) * 1989-01-30 1990-08-08 Hitachi Ltd 半導体装置およびその製造方法
NL8903158A (nl) * 1989-12-27 1991-07-16 Philips Nv Werkwijze voor het contacteren van silicidesporen.
JP3044849B2 (ja) * 1991-07-30 2000-05-22 ソニー株式会社 半導体装置の製造方法
US5173450A (en) * 1991-12-30 1992-12-22 Texas Instruments Incorporated Titanium silicide local interconnect process

Also Published As

Publication number Publication date
EP0572214A3 (de) 1994-01-12
EP0572214A2 (de) 1993-12-01
US5313084A (en) 1994-05-17
JPH06177132A (ja) 1994-06-24
US5346860A (en) 1994-09-13
EP0572214B1 (de) 1998-02-18
DE69317012T2 (de) 1998-06-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee