DE69320743D1 - Halbleiterspeichergerät mit Redundanz - Google Patents

Halbleiterspeichergerät mit Redundanz

Info

Publication number
DE69320743D1
DE69320743D1 DE69320743T DE69320743T DE69320743D1 DE 69320743 D1 DE69320743 D1 DE 69320743D1 DE 69320743 T DE69320743 T DE 69320743T DE 69320743 T DE69320743 T DE 69320743T DE 69320743 D1 DE69320743 D1 DE 69320743D1
Authority
DE
Germany
Prior art keywords
redundancy
storage device
semiconductor storage
semiconductor
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69320743T
Other languages
English (en)
Other versions
DE69320743T2 (de
Inventor
Yoshinori Matsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69320743D1 publication Critical patent/DE69320743D1/de
Application granted granted Critical
Publication of DE69320743T2 publication Critical patent/DE69320743T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
DE69320743T 1992-09-29 1993-09-28 Halbleiterspeichergerät mit Redundanz Expired - Fee Related DE69320743T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26004992A JP2870320B2 (ja) 1992-09-29 1992-09-29 半導体メモリ回路

Publications (2)

Publication Number Publication Date
DE69320743D1 true DE69320743D1 (de) 1998-10-08
DE69320743T2 DE69320743T2 (de) 1999-05-06

Family

ID=17342599

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69320743T Expired - Fee Related DE69320743T2 (de) 1992-09-29 1993-09-28 Halbleiterspeichergerät mit Redundanz

Country Status (5)

Country Link
US (1) US5424987A (de)
EP (1) EP0590608B1 (de)
JP (1) JP2870320B2 (de)
KR (1) KR960016500B1 (de)
DE (1) DE69320743T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9417269D0 (en) * 1994-08-26 1994-10-19 Inmos Ltd Memory and test method therefor
DE69616747T2 (de) * 1996-03-29 2002-08-08 St Microelectronics Srl Redundanzverwaltungsverfahren und -architektur, insbesondere für nicht-flüchtige Speicher
US6243289B1 (en) 1998-04-08 2001-06-05 Micron Technology Inc. Dual floating gate programmable read only memory cell structure and method for its fabrication and operation
WO2000063478A1 (en) * 1999-04-19 2000-10-26 E.I. Du Pont De Nemours And Company A stretch recoverable nonwoven fabric and a process for making
US6985391B2 (en) * 2004-05-07 2006-01-10 Micron Technology, Inc. High speed redundant data sensing method and apparatus
JP2011113620A (ja) * 2009-11-27 2011-06-09 Elpida Memory Inc 半導体装置及びこれを備えるデータ処理システム

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58137192A (ja) * 1981-12-29 1983-08-15 Fujitsu Ltd 半導体記憶装置
JPS58200571A (ja) * 1982-05-18 1983-11-22 Matsushita Electric Ind Co Ltd 半導体記憶装置
US4601019B1 (en) * 1983-08-31 1997-09-30 Texas Instruments Inc Memory with redundancy
US4691300A (en) 1985-12-20 1987-09-01 Motorola, Inc. Redundant column substitution architecture with improved column access time
KR890003691B1 (ko) * 1986-08-22 1989-09-30 삼성전자 주식회사 블럭 열 리던던씨 회로
JPS63239696A (ja) * 1987-03-27 1988-10-05 Toshiba Corp 冗長回路付メモリの試験装置
JPH073754B2 (ja) * 1988-03-08 1995-01-18 三菱電機株式会社 半導体記憶装置
JP2776835B2 (ja) * 1988-07-08 1998-07-16 株式会社日立製作所 欠陥救済用の冗長回路を有する半導体メモリ
JP2837433B2 (ja) * 1989-06-05 1998-12-16 三菱電機株式会社 半導体記憶装置における不良ビット救済回路
EP0411626B1 (de) * 1989-08-04 1995-10-25 Fujitsu Limited Halbleiterspeichergerät mit Redundanz
JP2737293B2 (ja) * 1989-08-30 1998-04-08 日本電気株式会社 Ｍｏｓ型半導体記憶装置
KR920009059B1 (ko) * 1989-12-29 1992-10-13 삼성전자 주식회사 반도체 메모리 장치의 병렬 테스트 방법
JP2853406B2 (ja) * 1991-09-10 1999-02-03 日本電気株式会社 半導体記憶装置

Also Published As

Publication number Publication date
KR960016500B1 (ko) 1996-12-12
KR940007897A (ko) 1994-04-28
EP0590608A2 (de) 1994-04-06
EP0590608A3 (de) 1994-12-14
JP2870320B2 (ja) 1999-03-17
US5424987A (en) 1995-06-13
EP0590608B1 (de) 1998-09-02
DE69320743T2 (de) 1999-05-06
JPH06111598A (ja) 1994-04-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee