DE69326658D1 - Individuelle Stromversorgung für die Schaltungen auf einer Wafer vor dem Teilvorgang - Google Patents

Individuelle Stromversorgung für die Schaltungen auf einer Wafer vor dem Teilvorgang

Info

Publication number
DE69326658D1
DE69326658D1 DE69326658T DE69326658T DE69326658D1 DE 69326658 D1 DE69326658 D1 DE 69326658D1 DE 69326658 T DE69326658 T DE 69326658T DE 69326658 T DE69326658 T DE 69326658T DE 69326658 D1 DE69326658 D1 DE 69326658D1
Authority
DE
Germany
Prior art keywords
circuits
sub
power supply
individual power
wafer before
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69326658T
Other languages
English (en)
Inventor
Michael D Rostoker
Carlos Dangelo
James Koford
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Corp filed Critical LSI Logic Corp
Application granted granted Critical
Publication of DE69326658D1 publication Critical patent/DE69326658D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/028—Dicing
DE69326658T 1992-07-02 1993-07-01 Individuelle Stromversorgung für die Schaltungen auf einer Wafer vor dem Teilvorgang Expired - Lifetime DE69326658D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/908,695 US5389556A (en) 1992-07-02 1992-07-02 Individually powering-up unsingulated dies on a wafer

Publications (1)

Publication Number Publication Date
DE69326658D1 true DE69326658D1 (de) 1999-11-11

Family

ID=25426126

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69326658T Expired - Lifetime DE69326658D1 (de) 1992-07-02 1993-07-01 Individuelle Stromversorgung für die Schaltungen auf einer Wafer vor dem Teilvorgang

Country Status (4)

Country Link
US (1) US5389556A (de)
EP (1) EP0583585B1 (de)
JP (1) JPH0677297A (de)
DE (1) DE69326658D1 (de)

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US5878486A (en) * 1993-11-16 1999-03-09 Formfactor, Inc. Method of burning-in semiconductor devices
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US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6429677B1 (en) * 2000-02-10 2002-08-06 International Business Machines Corporation Method and apparatus for characterization of gate dielectrics
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DE10133261A1 (de) * 2001-07-09 2003-01-30 Infineon Technologies Ag Vorrichtung zum unabhängigen Testen mehrerer spannungsversorgter Halbleitereinrichtungen
US6809378B2 (en) * 2001-08-30 2004-10-26 Micron Technology, Inc. Structure for temporarily isolating a die from a common conductor to facilitate wafer level testing
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DE10152086B4 (de) * 2001-10-23 2007-03-22 Infineon Technologies Ag Verfahren zum Testen einer Mehrzahl von Bauelementen auf einem Wafer mit einer gemeinsamen Datenleitung und einer gemeinsamen Versorgungsleitung
KR100496862B1 (ko) * 2002-10-01 2005-06-22 삼성전자주식회사 멀티칩패키지의 테스트 장치 및 방법
DE10310140B4 (de) * 2003-03-07 2007-05-03 Infineon Technologies Ag Testvorrichtung zum Test von integrierten Bausteinen sowie Verfahren zum Betrieb einer Testvorrichtung
KR100523139B1 (ko) * 2003-06-23 2005-10-20 주식회사 하이닉스반도체 웨이퍼 테스트시 사용되는 프로빙 패드의 수를 감소시키기위한 반도체 장치 및 그의 테스팅 방법
US7057249B2 (en) * 2003-07-02 2006-06-06 Hewlett-Packard Development Company, L.P. Magnetic memory device
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US7365556B2 (en) * 2004-09-02 2008-04-29 Texas Instruments Incorporated Semiconductor device testing
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US7405585B2 (en) * 2006-02-14 2008-07-29 Taiwan Semiconductor Manufacturing Co., Ltd. Versatile semiconductor test structure array
US7888955B2 (en) * 2007-09-25 2011-02-15 Formfactor, Inc. Method and apparatus for testing devices using serially controlled resources
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US20090164931A1 (en) * 2007-12-19 2009-06-25 Formfactor, Inc. Method and Apparatus for Managing Test Result Data Generated by a Semiconductor Test System
US20090224793A1 (en) * 2008-03-07 2009-09-10 Formfactor, Inc. Method And Apparatus For Designing A Custom Test System
US8122309B2 (en) * 2008-03-11 2012-02-21 Formfactor, Inc. Method and apparatus for processing failures during semiconductor device testing
US8095841B2 (en) * 2008-08-19 2012-01-10 Formfactor, Inc. Method and apparatus for testing semiconductor devices with autonomous expected value generation
US7944225B2 (en) 2008-09-26 2011-05-17 Formfactor, Inc. Method and apparatus for providing a tester integrated circuit for testing a semiconductor device under test
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US9157954B2 (en) * 2011-06-03 2015-10-13 Apple Inc. Test system with temporary test structures
US8890557B2 (en) 2012-04-10 2014-11-18 International Business Machines Corporation Built-in self-test method and structure
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Also Published As

Publication number Publication date
JPH0677297A (ja) 1994-03-18
EP0583585A2 (de) 1994-02-23
EP0583585B1 (de) 1999-10-06
EP0583585A3 (de) 1995-02-15
US5389556A (en) 1995-02-14

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Legal Events

Date Code Title Description
8332 No legal effect for de