DE69329592D1 - Multiprozessor-System zur Übertragung von in Netzwerkgerät erzeugten Anomalienerkennungssignalen zurück zum Prozessor parallel mit dem Datenübertragungsweg - Google Patents
Multiprozessor-System zur Übertragung von in Netzwerkgerät erzeugten Anomalienerkennungssignalen zurück zum Prozessor parallel mit dem DatenübertragungswegInfo
- Publication number
- DE69329592D1 DE69329592D1 DE69329592T DE69329592T DE69329592D1 DE 69329592 D1 DE69329592 D1 DE 69329592D1 DE 69329592 T DE69329592 T DE 69329592T DE 69329592 T DE69329592 T DE 69329592T DE 69329592 D1 DE69329592 D1 DE 69329592D1
- Authority
- DE
- Germany
- Prior art keywords
- data processing
- abnormality detection
- data transfer
- detection signal
- processing apparatuses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0766—Error or fault reporting or storing
- G06F11/0772—Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
- G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32003092A JP3461520B2 (ja) | 1992-11-30 | 1992-11-30 | マルチプロセッサシステム |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69329592D1 true DE69329592D1 (de) | 2000-11-30 |
DE69329592T2 DE69329592T2 (de) | 2001-03-15 |
Family
ID=18116969
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69329592T Expired - Fee Related DE69329592T2 (de) | 1992-11-30 | 1993-08-18 | Multiprozessor-System zur Übertragung von in Netzwerkgerät erzeugten Anomalienerkennungssignalen zurück zum Prozessor parallel mit dem Datenübertragungsweg |
Country Status (4)
Country | Link |
---|---|
US (1) | US5572679A (de) |
EP (1) | EP0600581B1 (de) |
JP (1) | JP3461520B2 (de) |
DE (1) | DE69329592T2 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3459056B2 (ja) * | 1996-11-08 | 2003-10-20 | 株式会社日立製作所 | データ転送システム |
IL142400A0 (en) * | 1998-09-18 | 2002-03-10 | Harris Corp | Distributed trunking mechanism for vhf networking |
US7020077B2 (en) * | 2000-09-29 | 2006-03-28 | Alcatel | Cross-connect matrix task prioritizer |
US20030005154A1 (en) * | 2001-06-29 | 2003-01-02 | Thurman Robert W. | Shared routing in a measurement system |
US6892321B2 (en) * | 2001-07-17 | 2005-05-10 | International Business Machines Corporation | Transition to switch node adapter diagnostics using adapter device driver |
US6848062B1 (en) | 2001-12-21 | 2005-01-25 | Ciena Corporation | Mesh protection service in a communications network |
JP4087179B2 (ja) * | 2002-07-29 | 2008-05-21 | 富士通株式会社 | 加入者線端局装置 |
GB2398650B (en) * | 2003-02-21 | 2006-09-20 | Picochip Designs Ltd | Communications in a processor array |
JP2012128697A (ja) * | 2010-12-16 | 2012-07-05 | Hitachi Ltd | 情報処理装置 |
JP6841362B1 (ja) | 2020-03-17 | 2021-03-10 | 住友大阪セメント株式会社 | リチウムイオン二次電池用正極材料、リチウムイオン二次電池用正極及びリチウムイオン二次電池 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5161156A (en) * | 1990-02-02 | 1992-11-03 | International Business Machines Corporation | Multiprocessing packet switching connection system having provision for error correction and recovery |
EP0505781B1 (de) * | 1991-03-29 | 2001-10-17 | International Business Machines Corporation | Serieller Multimedia Linienschalter für Parallelnetzwerke und ein heterogenes homologes Rechnersystem |
US5321813A (en) * | 1991-05-01 | 1994-06-14 | Teradata Corporation | Reconfigurable, fault tolerant, multistage interconnect network and protocol |
US5345229A (en) * | 1992-09-17 | 1994-09-06 | International Business Machines Corporation | Adaptive switching apparatus for multi-stage networks |
-
1992
- 1992-11-30 JP JP32003092A patent/JP3461520B2/ja not_active Expired - Fee Related
-
1993
- 1993-08-12 US US08/105,174 patent/US5572679A/en not_active Expired - Lifetime
- 1993-08-18 EP EP93306517A patent/EP0600581B1/de not_active Expired - Lifetime
- 1993-08-18 DE DE69329592T patent/DE69329592T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0600581A2 (de) | 1994-06-08 |
US5572679A (en) | 1996-11-05 |
EP0600581A3 (en) | 1997-03-05 |
JPH06168218A (ja) | 1994-06-14 |
EP0600581B1 (de) | 2000-10-25 |
DE69329592T2 (de) | 2001-03-15 |
JP3461520B2 (ja) | 2003-10-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |