DE69334165D1 - Netzwerkanpassungseinrichtung mit hauptrechnerunterbrechung und indikationsverwaltung - Google Patents

Netzwerkanpassungseinrichtung mit hauptrechnerunterbrechung und indikationsverwaltung

Info

Publication number
DE69334165D1
DE69334165D1 DE69334165T DE69334165T DE69334165D1 DE 69334165 D1 DE69334165 D1 DE 69334165D1 DE 69334165 T DE69334165 T DE 69334165T DE 69334165 T DE69334165 T DE 69334165T DE 69334165 D1 DE69334165 D1 DE 69334165D1
Authority
DE
Germany
Prior art keywords
memory location
host
interrupt
indication
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69334165T
Other languages
English (en)
Other versions
DE69334165T2 (de
Inventor
Scott Andrew Emery
Brian Petersen
W Paul Sherer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3Com Corp
Original Assignee
3Com Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=21755544&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69334165(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by 3Com Corp filed Critical 3Com Corp
Application granted granted Critical
Publication of DE69334165D1 publication Critical patent/DE69334165D1/de
Publication of DE69334165T2 publication Critical patent/DE69334165T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
DE69334165T 1993-02-02 1993-12-28 Netzwerkanpassungseinrichtung mit hauptrechnerunterbrechung und indikationsverwaltung Expired - Lifetime DE69334165T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/012,561 US5530874A (en) 1993-02-02 1993-02-02 Network adapter with an indication signal mask and an interrupt signal mask
US12561 1993-02-02
PCT/US1993/012652 WO1994018627A2 (en) 1993-02-02 1993-12-28 Network adapter with host interrupt and indication management

Publications (2)

Publication Number Publication Date
DE69334165D1 true DE69334165D1 (de) 2007-10-18
DE69334165T2 DE69334165T2 (de) 2008-05-29

Family

ID=21755544

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69334165T Expired - Lifetime DE69334165T2 (de) 1993-02-02 1993-12-28 Netzwerkanpassungseinrichtung mit hauptrechnerunterbrechung und indikationsverwaltung

Country Status (9)

Country Link
US (1) US5530874A (de)
EP (1) EP0682791B1 (de)
JP (1) JPH08506674A (de)
KR (1) KR0161101B1 (de)
AT (1) ATE372552T1 (de)
AU (1) AU675501B2 (de)
CA (1) CA2152392C (de)
DE (1) DE69334165T2 (de)
WO (1) WO1994018627A2 (de)

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US5412782A (en) 1992-07-02 1995-05-02 3Com Corporation Programmed I/O ethernet adapter with early interrupts for accelerating data transfer
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US5797037A (en) * 1995-03-31 1998-08-18 Cirrus Logic, Inc. Interrupt request control logic reducing the number of interrupts required for I/O data transfer
JP2625402B2 (ja) * 1995-05-24 1997-07-02 日本電気株式会社 マイクロプロセッサ
US5740448A (en) * 1995-07-07 1998-04-14 Sun Microsystems, Inc. Method and apparatus for exclusive access to shared data structures through index referenced buffers
US5909582A (en) * 1996-04-26 1999-06-01 Nec Corporation Microcomputer having user mode interrupt function and supervisor mode interrupt function
US5970229A (en) * 1996-09-12 1999-10-19 Cabletron Systems, Inc. Apparatus and method for performing look-ahead scheduling of DMA transfers of data from a host memory to a transmit buffer memory
US5995995A (en) * 1996-09-12 1999-11-30 Cabletron Systems, Inc. Apparatus and method for scheduling virtual circuit data for DMA from a host memory to a transmit buffer memory
US5999980A (en) * 1996-09-12 1999-12-07 Cabletron Systems, Inc. Apparatus and method for setting a congestion indicate bit in an backwards RM cell on an ATM network
US5941952A (en) * 1996-09-12 1999-08-24 Cabletron Systems, Inc. Apparatus and method for transferring data from a transmit buffer memory at a particular rate
US5966546A (en) 1996-09-12 1999-10-12 Cabletron Systems, Inc. Method and apparatus for performing TX raw cell status report frequency and interrupt frequency mitigation in a network node
US5922046A (en) * 1996-09-12 1999-07-13 Cabletron Systems, Inc. Method and apparatus for avoiding control reads in a network node
US5881296A (en) * 1996-10-02 1999-03-09 Intel Corporation Method for improved interrupt processing in a computer system
US5854908A (en) * 1996-10-15 1998-12-29 International Business Machines Corporation Computer system generating a processor interrupt in response to receiving an interrupt/data synchronizing signal over a data bus
US6115776A (en) * 1996-12-05 2000-09-05 3Com Corporation Network and adaptor with time-based and packet number based interrupt combinations
US6012121A (en) * 1997-04-08 2000-01-04 International Business Machines Corporation Apparatus for flexible control of interrupts in multiprocessor systems
US6098104A (en) * 1997-04-08 2000-08-01 International Business Machines Corporation Source and destination initiated interrupts for message arrival notification, and related data structures
US6105071A (en) * 1997-04-08 2000-08-15 International Business Machines Corporation Source and destination initiated interrupt system for message arrival notification
US6098105A (en) * 1997-04-08 2000-08-01 International Business Machines Corporation Source and destination initiated interrupt method for message arrival notification
US5875342A (en) * 1997-06-03 1999-02-23 International Business Machines Corporation User programmable interrupt mask with timeout
US6243785B1 (en) * 1998-05-20 2001-06-05 3Com Corporation Hardware assisted polling for software drivers
US6351785B1 (en) * 1999-01-26 2002-02-26 3Com Corporation Interrupt optimization using varying quantity threshold
US6189066B1 (en) * 1999-01-26 2001-02-13 3Com Corporation System and method for dynamically selecting interrupt time interval threshold parameters
US6529986B1 (en) * 1999-01-26 2003-03-04 3Com Corporation Interrupt optimization using storage time for peripheral component events
US6189067B1 (en) * 1999-01-26 2001-02-13 3Com Corporation System and method for dynamically selecting interrupt quantity threshold parameters
US6192440B1 (en) * 1999-01-26 2001-02-20 3Com Corporation System and method for dynamically selecting interrupt storage time threshold parameters
US6574694B1 (en) * 1999-01-26 2003-06-03 3Com Corporation Interrupt optimization using time between succeeding peripheral component events
US6137734A (en) * 1999-03-30 2000-10-24 Lsi Logic Corporation Computer memory interface having a memory controller that automatically adjusts the timing of memory interface signals
US6526514B1 (en) * 1999-10-11 2003-02-25 Ati International Srl Method and apparatus for power management interrupt processing in a computing system
US6754755B1 (en) * 2000-08-10 2004-06-22 Hewlett-Packard Development Company, L.P. Service request system using an activity indicator to reduce processing overhead
US6889278B1 (en) * 2001-04-04 2005-05-03 Cisco Technology, Inc. Method and apparatus for fast acknowledgement and efficient servicing of interrupt sources coupled to high latency paths
EP1474067B2 (de) 2001-07-02 2017-08-16 Zoetis Services LLC Vakzination in einer dosis mit i mycoplasma hyopneumoniae /i
US20040128418A1 (en) * 2002-12-30 2004-07-01 Darren Abramson Mechanism and apparatus for SMI generation
US7389496B2 (en) * 2003-07-02 2008-06-17 Agere Systems Inc. Condition management system and a method of operation thereof
US7596779B2 (en) * 2004-02-19 2009-09-29 Agere Systems Inc. Condition management callback system and method of operation thereof
US20120166687A1 (en) * 2010-12-22 2012-06-28 Stmicroelectronics, Inc. Computer Architecture Using Shadow Hardware
US11476928B2 (en) 2020-03-18 2022-10-18 Mellanox Technologies, Ltd. TDMA networking using commodity NIC/switch
US11336383B2 (en) 2020-06-24 2022-05-17 Mellanox Technologies, Ltd. Packet scheduling system with desired physical transmission time for packets
US11388263B2 (en) 2020-10-11 2022-07-12 Mellanox Technologies, Ltd. Packet transmission using scheduled prefetching
US11711158B2 (en) 2021-06-28 2023-07-25 Mellanox Technologies, Ltd. Accurate time-stamping of outbound packets

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JPS55123736A (en) * 1979-03-16 1980-09-24 Hitachi Ltd Interrupt control system
GB2212291B (en) * 1980-08-14 1989-11-29 Marconi Co Ltd Sighting system
US4807117A (en) * 1983-07-19 1989-02-21 Nec Corporation Interruption control apparatus
US4631659A (en) * 1984-03-08 1986-12-23 Texas Instruments Incorporated Memory interface with automatic delay state
JPS619748A (ja) * 1984-06-25 1986-01-17 Nec Corp 入出力制御装置
JPS6118059A (ja) * 1984-07-05 1986-01-25 Nec Corp メモリ回路
US4768149A (en) * 1985-08-29 1988-08-30 International Business Machines Corporation System for managing a plurality of shared interrupt handlers in a linked-list data structure
US4933846A (en) * 1987-04-24 1990-06-12 Network Systems Corporation Network communications adapter with dual interleaved memory banks servicing multiple processors
JPH01126751A (ja) * 1987-11-11 1989-05-18 Fujitsu Ltd グルーピング装置
JPH0769783B2 (ja) * 1987-11-16 1995-07-31 日本電気株式会社 例外処理方式
US5161228A (en) * 1988-03-02 1992-11-03 Ricoh Company, Ltd. System with selectively exclusionary enablement for plural indirect address type interrupt control circuit
JP2591181B2 (ja) * 1989-09-22 1997-03-19 日本電気株式会社 マイクロコンピュータ
JP2855298B2 (ja) * 1990-12-21 1999-02-10 インテル・コーポレーション 割込み要求の仲裁方法およびマルチプロセッサシステム
US5179704A (en) * 1991-03-13 1993-01-12 Ncr Corporation Method and apparatus for generating disk array interrupt signals
EP0584257B1 (de) * 1991-05-17 2004-08-04 Packard Bell NEC, Inc. Leistungsmanagementsfunktion für einen rückwärtskompatiblen mikroprozessor
JP3176093B2 (ja) * 1991-09-05 2001-06-11 日本電気株式会社 マイクロプロセッサの割込み制御装置
US5319752A (en) * 1992-09-18 1994-06-07 3Com Corporation Device with host indication combination

Also Published As

Publication number Publication date
JPH08506674A (ja) 1996-07-16
WO1994018627A2 (en) 1994-08-18
EP0682791A1 (de) 1995-11-22
WO1994018627A3 (en) 1994-09-29
DE69334165T2 (de) 2008-05-29
CA2152392C (en) 2000-11-07
EP0682791A4 (de) 1999-02-03
EP0682791B1 (de) 2007-09-05
KR0161101B1 (ko) 1999-01-15
AU675501B2 (en) 1997-02-06
KR960700479A (ko) 1996-01-20
AU5987394A (en) 1994-08-29
ATE372552T1 (de) 2007-09-15
CA2152392A1 (en) 1994-08-18
US5530874A (en) 1996-06-25

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