DE69413665T2 - Passivierungsverfahren für eine ferroelektrische integrierte Schaltung, das harte keramische Materialien benutzt - Google Patents

Passivierungsverfahren für eine ferroelektrische integrierte Schaltung, das harte keramische Materialien benutzt

Info

Publication number
DE69413665T2
DE69413665T2 DE69413665T DE69413665T DE69413665T2 DE 69413665 T2 DE69413665 T2 DE 69413665T2 DE 69413665 T DE69413665 T DE 69413665T DE 69413665 T DE69413665 T DE 69413665T DE 69413665 T2 DE69413665 T2 DE 69413665T2
Authority
DE
Germany
Prior art keywords
integrated circuit
ceramic materials
passivation process
hard ceramic
ferroelectric integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69413665T
Other languages
English (en)
Other versions
DE69413665D1 (de
Inventor
George Argos
John D Spano
Steven D Traynor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ramtron International Corp
Original Assignee
Ramtron International Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ramtron International Corp filed Critical Ramtron International Corp
Application granted granted Critical
Publication of DE69413665D1 publication Critical patent/DE69413665D1/de
Publication of DE69413665T2 publication Critical patent/DE69413665T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/958—Passivation layer
DE69413665T 1994-03-11 1994-12-09 Passivierungsverfahren für eine ferroelektrische integrierte Schaltung, das harte keramische Materialien benutzt Expired - Fee Related DE69413665T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/212,495 US5438023A (en) 1994-03-11 1994-03-11 Passivation method and structure for a ferroelectric integrated circuit using hard ceramic materials or the like

Publications (2)

Publication Number Publication Date
DE69413665D1 DE69413665D1 (de) 1998-11-05
DE69413665T2 true DE69413665T2 (de) 1999-06-17

Family

ID=22791262

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69413665T Expired - Fee Related DE69413665T2 (de) 1994-03-11 1994-12-09 Passivierungsverfahren für eine ferroelektrische integrierte Schaltung, das harte keramische Materialien benutzt

Country Status (4)

Country Link
US (2) US5438023A (de)
EP (1) EP0671765B1 (de)
JP (1) JP2921556B2 (de)
DE (1) DE69413665T2 (de)

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Also Published As

Publication number Publication date
EP0671765A1 (de) 1995-09-13
EP0671765B1 (de) 1998-09-30
US5578867A (en) 1996-11-26
US5438023A (en) 1995-08-01
JP2921556B2 (ja) 1999-07-19
JPH0855850A (ja) 1996-02-27
DE69413665D1 (de) 1998-11-05

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