DE69424221D1 - Mehrrechnersystem - Google Patents

Mehrrechnersystem

Info

Publication number
DE69424221D1
DE69424221D1 DE69424221T DE69424221T DE69424221D1 DE 69424221 D1 DE69424221 D1 DE 69424221D1 DE 69424221 T DE69424221 T DE 69424221T DE 69424221 T DE69424221 T DE 69424221T DE 69424221 D1 DE69424221 D1 DE 69424221D1
Authority
DE
Germany
Prior art keywords
computer system
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69424221T
Other languages
English (en)
Inventor
Bruno Conterno
Mauro Gismondi
Vildo Luperini
Fernando Pesce
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Selex Elsag Datamat SpA
Original Assignee
Elsag SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elsag SpA filed Critical Elsag SpA
Application granted granted Critical
Publication of DE69424221D1 publication Critical patent/DE69424221D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
DE69424221T 1993-06-11 1994-06-09 Mehrrechnersystem Expired - Lifetime DE69424221D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITTO930428A IT1260848B (it) 1993-06-11 1993-06-11 Sistema a multiprocessore

Publications (1)

Publication Number Publication Date
DE69424221D1 true DE69424221D1 (de) 2000-06-08

Family

ID=11411555

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69424221T Expired - Lifetime DE69424221D1 (de) 1993-06-11 1994-06-09 Mehrrechnersystem

Country Status (4)

Country Link
US (1) US5586258A (de)
EP (1) EP0628917B1 (de)
DE (1) DE69424221D1 (de)
IT (1) IT1260848B (de)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
WO2002071196A2 (de) * 2001-03-05 2002-09-12 Pact Informationstechnologie Gmbh Verfahren und vorrichtung zu datenbe- und/oder verarbeitung
DE19651075A1 (de) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
EP1329816B1 (de) 1996-12-27 2011-06-22 Richter, Thomas Verfahren zum selbständigen dynamischen Umladen von Datenflussprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o.dgl.)
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
US6212606B1 (en) * 1998-10-13 2001-04-03 Compaq Computer Corporation Computer system and method for establishing a standardized shared level for each storage unit
WO2000077652A2 (de) 1999-06-10 2000-12-21 Pact Informationstechnologie Gmbh Sequenz-partitionierung auf zellstrukturen
US6973559B1 (en) * 1999-09-29 2005-12-06 Silicon Graphics, Inc. Scalable hypercube multiprocessor network for massive parallel processing
EP2226732A3 (de) 2000-06-13 2016-04-06 PACT XPP Technologies AG Cachehierarchie für einen Multicore-Prozessor
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
JP4783527B2 (ja) 2001-01-31 2011-09-28 株式会社ガイア・システム・ソリューション データ処理システム、データ処理装置およびその制御方法
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
WO2005045692A2 (en) 2003-08-28 2005-05-19 Pact Xpp Technologies Ag Data processing device and method
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7657877B2 (en) 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data
JP4865960B2 (ja) 2001-06-25 2012-02-01 株式会社ガイア・システム・ソリューション データ処理装置およびその制御方法
US7996827B2 (en) * 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US6993674B2 (en) 2001-12-27 2006-01-31 Pacific Design, Inc. System LSI architecture and method for controlling the clock of a data processing system through the use of instructions
AU2003208266A1 (en) 2002-01-19 2003-07-30 Pact Xpp Technologies Ag Reconfigurable processor
AU2003214003A1 (en) 2002-02-18 2003-09-09 Pact Xpp Technologies Ag Bus systems and method for reconfiguration
US7085866B1 (en) * 2002-02-19 2006-08-01 Hobson Richard F Hierarchical bus structure and memory access protocol for multiprocessor systems
US6959372B1 (en) * 2002-02-19 2005-10-25 Cogent Chipware Inc. Processor cluster architecture and associated parallel processing methods
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
WO2004021176A2 (de) 2002-08-07 2004-03-11 Pact Xpp Technologies Ag Verfahren und vorrichtung zur datenverarbeitung
US7394284B2 (en) 2002-09-06 2008-07-01 Pact Xpp Technologies Ag Reconfigurable sequencer structure
WO2007082730A1 (de) 2006-01-18 2007-07-26 Pact Xpp Technologies Ag Hardwaredefinitionsverfahren
US20120096292A1 (en) * 2010-10-15 2012-04-19 Mosaid Technologies Incorporated Method, system and apparatus for multi-level processing
RU2623806C1 (ru) * 2016-06-07 2017-06-29 Акционерное общество Научно-производственный центр "Электронные вычислительно-информационные системы" (АО НПЦ "ЭЛВИС") Способ и устройство обработки стереоизображений

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4130865A (en) * 1974-06-05 1978-12-19 Bolt Beranek And Newman Inc. Multiprocessor computer apparatus employing distributed communications paths and a passive task register
WO1983001135A1 (en) * 1981-09-18 1983-03-31 Rovsing As Christian Multiprocessor computer system
US4485438A (en) * 1982-06-28 1984-11-27 Myrmo Erik R High transfer rate between multi-processor units
IT1184015B (it) * 1985-12-13 1987-10-22 Elsag Sistema multiprocessore a piu livelli gerarchici
US4734865A (en) * 1986-01-28 1988-03-29 Bell & Howell Company Insertion machine with audit trail and command protocol
US4942575A (en) * 1988-06-17 1990-07-17 Modular Computer Systems, Inc. Error connection device for parity protected memory systems
US4912633A (en) * 1988-10-24 1990-03-27 Ncr Corporation Hierarchical multiple bus computer architecture
DE69231451T2 (de) * 1991-03-11 2001-05-10 Mips Tech Inc Rückwärts kompatible Rechnerarchitektur mit erweiterten Wortbreiten und Adressraum

Also Published As

Publication number Publication date
ITTO930428A0 (it) 1993-06-11
US5586258A (en) 1996-12-17
IT1260848B (it) 1996-04-23
ITTO930428A1 (it) 1994-12-11
EP0628917A2 (de) 1994-12-14
EP0628917A3 (de) 1995-08-09
EP0628917B1 (de) 2000-05-03

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Legal Events

Date Code Title Description
8332 No legal effect for de