DE69427443D1 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69427443D1
DE69427443D1 DE69427443T DE69427443T DE69427443D1 DE 69427443 D1 DE69427443 D1 DE 69427443D1 DE 69427443 T DE69427443 T DE 69427443T DE 69427443 T DE69427443 T DE 69427443T DE 69427443 D1 DE69427443 D1 DE 69427443D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69427443T
Other languages
English (en)
Other versions
DE69427443T2 (de
Inventor
Shigeo Chishiki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=17537585&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69427443(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69427443D1 publication Critical patent/DE69427443D1/de
Application granted granted Critical
Publication of DE69427443T2 publication Critical patent/DE69427443T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
DE69427443T 1993-11-02 1994-10-26 Halbleiterspeicheranordnung Expired - Fee Related DE69427443T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5274140A JP2725570B2 (ja) 1993-11-02 1993-11-02 半導体メモリ装置

Publications (2)

Publication Number Publication Date
DE69427443D1 true DE69427443D1 (de) 2001-07-19
DE69427443T2 DE69427443T2 (de) 2002-04-18

Family

ID=17537585

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69427443T Expired - Fee Related DE69427443T2 (de) 1993-11-02 1994-10-26 Halbleiterspeicheranordnung

Country Status (5)

Country Link
US (1) US5517456A (de)
EP (1) EP0651393B1 (de)
JP (1) JP2725570B2 (de)
KR (1) KR0163778B1 (de)
DE (1) DE69427443T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0172333B1 (ko) * 1995-01-16 1999-03-30 김광호 반도체 메모리 장치의 전원 승압 회로
KR0145225B1 (ko) * 1995-04-27 1998-08-17 김광호 블럭 단위로 스트레스 가능한 회로
KR0164377B1 (ko) * 1995-07-15 1999-02-18 김광호 반도체 메모리장치의 서브워드라인 드라이버
JPH09120693A (ja) * 1995-08-22 1997-05-06 Mitsubishi Electric Corp 半導体記憶装置
JPH09161476A (ja) 1995-10-04 1997-06-20 Toshiba Corp 半導体メモリ及びそのテスト回路、並びにデ−タ転送システム
KR100204542B1 (ko) * 1995-11-09 1999-06-15 윤종용 멀티 서브워드라인 드라이버를 갖는 반도체 메모리장치
US5793383A (en) * 1996-05-31 1998-08-11 Townsend And Townsend And Crew Llp Shared bootstrap circuit
KR100227268B1 (ko) * 1996-07-18 1999-11-01 윤종용 멀티 뱅크 메모리장치
JP3291206B2 (ja) * 1996-09-17 2002-06-10 富士通株式会社 半導体記憶装置
US5748554A (en) 1996-12-20 1998-05-05 Rambus, Inc. Memory and method for sensing sub-groups of memory elements
JP3862346B2 (ja) * 1997-03-13 2006-12-27 富士通株式会社 駆動回路及びそれを利用した半導体記憶装置
US5764589A (en) * 1997-03-28 1998-06-09 International Business Machines Corporation Array row and column decoder apparatus and method
KR100268889B1 (ko) * 1997-10-28 2000-10-16 김영환 반도체 메모리 장치의 워드라인 구동회로
US7500075B1 (en) 2001-04-17 2009-03-03 Rambus Inc. Mechanism for enabling full data bus utilization without increasing data granularity
US6825841B2 (en) * 2001-09-07 2004-11-30 Rambus Inc. Granularity memory column access
KR100512936B1 (ko) * 2002-11-18 2005-09-07 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 배치방법
JP4035074B2 (ja) * 2003-03-18 2008-01-16 松下電器産業株式会社 半導体記憶回路のレイアウト方法
US8190808B2 (en) * 2004-08-17 2012-05-29 Rambus Inc. Memory device having staggered memory operations
US7280428B2 (en) 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
JP6091083B2 (ja) 2011-05-20 2017-03-08 株式会社半導体エネルギー研究所 記憶装置
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3033288A1 (de) * 1980-09-04 1982-04-08 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zur breitbandigen linearisierung von mikrowellenverstaerkern
JP3024687B2 (ja) * 1990-06-05 2000-03-21 三菱電機株式会社 半導体記憶装置
US5124951A (en) * 1990-09-26 1992-06-23 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with sequenced latched row line repeaters
JPH04243089A (ja) * 1991-01-17 1992-08-31 Nec Corp 半導体記憶装置
JPH04318392A (ja) * 1991-04-17 1992-11-09 Hitachi Ltd 半導体集積回路装置
KR950004853B1 (ko) * 1991-08-14 1995-05-15 삼성전자 주식회사 저전력용 블럭 선택 기능을 가지는 반도체 메모리 장치
KR0113252Y1 (ko) * 1991-12-24 1998-04-14 문정환 워드라인 전압 공급회로
JP2867774B2 (ja) * 1992-01-06 1999-03-10 日本電気株式会社 半導体メモリ装置

Also Published As

Publication number Publication date
JPH07130168A (ja) 1995-05-19
EP0651393A2 (de) 1995-05-03
EP0651393B1 (de) 2001-06-13
EP0651393A3 (de) 1995-09-20
KR0163778B1 (ko) 1999-02-01
DE69427443T2 (de) 2002-04-18
JP2725570B2 (ja) 1998-03-11
KR950015389A (ko) 1995-06-16
US5517456A (en) 1996-05-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee