DE69427914T2 - Gegen äussere eingriffe gesicherte integrierte schaltungsanordnung - Google Patents

Gegen äussere eingriffe gesicherte integrierte schaltungsanordnung

Info

Publication number
DE69427914T2
DE69427914T2 DE69427914T DE69427914T DE69427914T2 DE 69427914 T2 DE69427914 T2 DE 69427914T2 DE 69427914 T DE69427914 T DE 69427914T DE 69427914 T DE69427914 T DE 69427914T DE 69427914 T2 DE69427914 T2 DE 69427914T2
Authority
DE
Germany
Prior art keywords
integrated circuit
circuit arrangement
against external
safe against
external intervention
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69427914T
Other languages
English (en)
Other versions
DE69427914D1 (de
Inventor
C Byrne
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Application granted granted Critical
Publication of DE69427914D1 publication Critical patent/DE69427914D1/de
Publication of DE69427914T2 publication Critical patent/DE69427914T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/922—Active solid-state devices, e.g. transistors, solid-state diodes with means to prevent inspection of or tampering with an integrated circuit, e.g. "smart card", anti-tamper
DE69427914T 1993-07-22 1994-06-24 Gegen äussere eingriffe gesicherte integrierte schaltungsanordnung Expired - Fee Related DE69427914T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/096,537 US5369299A (en) 1993-07-22 1993-07-22 Tamper resistant integrated circuit structure
PCT/US1994/007169 WO1995003627A1 (en) 1993-07-22 1994-06-24 Tamper resistant integrated circuit structure

Publications (2)

Publication Number Publication Date
DE69427914D1 DE69427914D1 (de) 2001-09-13
DE69427914T2 true DE69427914T2 (de) 2002-04-04

Family

ID=22257827

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69427914T Expired - Fee Related DE69427914T2 (de) 1993-07-22 1994-06-24 Gegen äussere eingriffe gesicherte integrierte schaltungsanordnung

Country Status (4)

Country Link
US (1) US5369299A (de)
EP (1) EP0710401B1 (de)
DE (1) DE69427914T2 (de)
WO (1) WO1995003627A1 (de)

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US5468990A (en) * 1993-07-22 1995-11-21 National Semiconductor Corp. Structures for preventing reverse engineering of integrated circuits
DE69514588T2 (de) * 1994-07-29 2000-06-21 St Microelectronics Inc Verfahren zum Testen und Reparieren eines integrierten Schaltkreises und zum Herstellen einer Passivierungsstruktur
US5783846A (en) * 1995-09-22 1998-07-21 Hughes Electronics Corporation Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering
US5719087A (en) * 1996-03-07 1998-02-17 Taiwan Semiconductor Manufacturing Company, Ltd. Process for bonding pad protection from damage
US5891354A (en) * 1996-07-26 1999-04-06 Fujitsu Limited Methods of etching through wafers and substrates with a composite etch stop layer
DE19634135C2 (de) * 1996-08-23 1998-07-02 Siemens Ag Halbleiterschaltung, insbesondere zur Verwendung in einem integrierten Baustein
US5863595A (en) * 1996-10-04 1999-01-26 Dow Corning Corporation Thick ceramic coatings for electronic devices
JP3587019B2 (ja) * 1997-04-08 2004-11-10 ソニー株式会社 半導体装置の製造方法
US5920081A (en) * 1997-04-25 1999-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Structure of a bond pad to prevent testing probe pin contamination
US5973375A (en) * 1997-06-06 1999-10-26 Hughes Electronics Corporation Camouflaged circuit structure with step implants
JP4033310B2 (ja) * 1997-12-16 2008-01-16 富士通株式会社 情報機器の補助記憶装置及び情報機器
US6875681B1 (en) * 1997-12-31 2005-04-05 Intel Corporation Wafer passivation structure and method of fabrication
JP3583633B2 (ja) * 1998-12-21 2004-11-04 シャープ株式会社 半導体装置の製造方法
US6160958A (en) * 1999-06-16 2000-12-12 Eastman Kodak Company Tamper resistant electronic flash unit for one-time-use camera
AU7483700A (en) * 1999-09-14 2001-04-17 Neopost, Inc. Method and apparatus for user-sealing of secured postage printing equipment
US6396368B1 (en) 1999-11-10 2002-05-28 Hrl Laboratories, Llc CMOS-compatible MEM switches and method of making
US6258705B1 (en) * 2000-08-21 2001-07-10 Siliconeware Precision Industries Co., Ltd. Method of forming circuit probing contact points on fine pitch peripheral bond pads on flip chip
US7217977B2 (en) 2004-04-19 2007-05-15 Hrl Laboratories, Llc Covert transformation of transistor properties as a circuit protection method
US6815816B1 (en) 2000-10-25 2004-11-09 Hrl Laboratories, Llc Implanted hidden interconnections in a semiconductor device for preventing reverse engineering
US6901343B2 (en) * 2001-01-10 2005-05-31 Matsushita Electric Industrial Co., Ltd. Multilayer board in which wiring of signal line that requires tamper-resistance is covered by component or foil, design apparatus, method, and program for the multilayer board, and medium recording the program
US6791191B2 (en) 2001-01-24 2004-09-14 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations
US7294935B2 (en) * 2001-01-24 2007-11-13 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide
US20020096744A1 (en) * 2001-01-24 2002-07-25 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using etched passivation openings in integrated circuits
US6774413B2 (en) 2001-06-15 2004-08-10 Hrl Laboratories, Llc Integrated circuit structure with programmable connector/isolator
US6740942B2 (en) 2001-06-15 2004-05-25 Hrl Laboratories, Llc. Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
US6897535B2 (en) 2002-05-14 2005-05-24 Hrl Laboratories, Llc Integrated circuit with reverse engineering protection
US7049667B2 (en) * 2002-09-27 2006-05-23 Hrl Laboratories, Llc Conductive channel pseudo block process and circuit to inhibit reverse engineering
US6979606B2 (en) 2002-11-22 2005-12-27 Hrl Laboratories, Llc Use of silicon block process step to camouflage a false transistor
AU2003293540A1 (en) 2002-12-13 2004-07-09 Raytheon Company Integrated circuit modification using well implants
US7242063B1 (en) 2004-06-29 2007-07-10 Hrl Laboratories, Llc Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
JP2006202938A (ja) * 2005-01-20 2006-08-03 Kojiro Kobayashi 半導体装置及びその製造方法
DE102005005622B4 (de) * 2005-02-08 2008-08-21 Infineon Technologies Ag Sicherheits-Chipstapel und ein Verfahren zum Herstellen eines Sicherheits-Chipstapels
EP1691413A1 (de) * 2005-02-11 2006-08-16 Axalto SA Falschungssichere elektronische Komponente
US7281667B2 (en) * 2005-04-14 2007-10-16 International Business Machines Corporation Method and structure for implementing secure multichip modules for encryption applications
US7402826B2 (en) * 2005-05-13 2008-07-22 Honeywell International Inc. System and method for non-destructively determining thickness and uniformity of anti-tamper coatings
US8168487B2 (en) 2006-09-28 2012-05-01 Hrl Laboratories, Llc Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer
DE102007046026A1 (de) 2007-09-26 2009-04-02 Rohde & Schwarz Sit Gmbh Schutzanordnung und Herstellungsverfahren für eine Schutzanordnung
US8188374B2 (en) 2008-07-16 2012-05-29 The Boeing Company Circuit obfuscation
GB0900082D0 (en) 2009-01-06 2009-02-11 Fulvens Ltd Method and apparatus for secure energy delivery
US8455990B2 (en) * 2009-02-25 2013-06-04 Conexant Systems, Inc. Systems and methods of tamper proof packaging of a semiconductor device
US8429471B2 (en) 2010-06-25 2013-04-23 Via Technologies, Inc. Microprocessor apparatus and method for securing a programmable fuse array
US8341472B2 (en) 2010-06-25 2012-12-25 Via Technologies, Inc. Apparatus and method for tamper protection of a microprocessor fuse array
US8242800B2 (en) 2010-06-25 2012-08-14 Via Technologies, Inc. Apparatus and method for override access to a secured programmable fuse array
US8451020B2 (en) 2010-09-30 2013-05-28 International Business Machines Corporation System and method for integrated circuit module tamperproof mode personalization
US9117126B2 (en) 2013-03-13 2015-08-25 Magtek, Inc. Tamper resistant 3D magnetic stripe reader integrated circuit
US9997492B2 (en) 2013-11-21 2018-06-12 Nxp Usa, Inc. Optically-masked microelectronic packages and methods for the fabrication thereof
FR3035267B1 (fr) 2015-04-20 2018-05-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Puce electronique comportant une face arriere protegee
US9942761B1 (en) 2016-10-10 2018-04-10 International Business Machines Corporation User access verification
US11748524B2 (en) 2020-07-20 2023-09-05 International Business Machines Corporation Tamper resistant obfuscation circuit
US11587890B2 (en) 2020-07-20 2023-02-21 International Business Machines Corporation Tamper-resistant circuit, back-end of the line memory and physical unclonable function for supply chain protection
US11877390B2 (en) * 2021-08-30 2024-01-16 International Business Machines Corporation Fabricating tamper-respondent sensors with random three-dimensional security patterns

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4030952A (en) * 1974-04-18 1977-06-21 Fairchild Camera And Instrument Corporation Method of MOS circuit fabrication
JP2579142B2 (ja) * 1984-08-22 1997-02-05 三菱電機株式会社 樹脂封止型半導体装置
DE3681689D1 (en) * 1985-10-22 1991-10-31 Siemens Ag, 8000 Muenchen, De Integrated semiconductor memory circuit for security or credit system
JPS63170944A (ja) * 1987-01-08 1988-07-14 Mitsubishi Electric Corp 半導体装置
JPH01165129A (ja) * 1987-12-21 1989-06-29 Sharp Corp 集積回路
EP0482247A1 (de) * 1990-10-26 1992-04-29 International Business Machines Corporation Verfahren zur Herstellung einer integrierten Schaltungsstruktur mit einer dicht mehrschichtigen Metallisierungsstruktur

Also Published As

Publication number Publication date
WO1995003627A1 (en) 1995-02-02
EP0710401B1 (de) 2001-08-08
US5369299A (en) 1994-11-29
DE69427914D1 (de) 2001-09-13
EP0710401A1 (de) 1996-05-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee