DE69432512D1 - Für fensterumgebungsoperationen entworfenes rasterpuffersystem - Google Patents

Für fensterumgebungsoperationen entworfenes rasterpuffersystem

Info

Publication number
DE69432512D1
DE69432512D1 DE69432512T DE69432512T DE69432512D1 DE 69432512 D1 DE69432512 D1 DE 69432512D1 DE 69432512 T DE69432512 T DE 69432512T DE 69432512 T DE69432512 T DE 69432512T DE 69432512 D1 DE69432512 D1 DE 69432512D1
Authority
DE
Germany
Prior art keywords
buffer system
system designed
grid buffer
environmental operations
window
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69432512T
Other languages
English (en)
Other versions
DE69432512T2 (de
Inventor
Curtis Priem
Chin Chang
Duy Ho
Cheng Sun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Semiconductor Inc
Sun Microsystems Inc
Original Assignee
Samsung Semiconductor Inc
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Semiconductor Inc, Sun Microsystems Inc filed Critical Samsung Semiconductor Inc
Application granted granted Critical
Publication of DE69432512D1 publication Critical patent/DE69432512D1/de
Publication of DE69432512T2 publication Critical patent/DE69432512T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/024—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour registers, e.g. to control background, foreground, surface filling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/022—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using memory planes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
DE69432512T 1993-10-29 1994-10-27 Für fensterumgebungsoperationen entworfenes rasterpuffersystem Expired - Fee Related DE69432512T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14533593A 1993-10-29 1993-10-29
US145335 1993-10-29
PCT/US1994/012307 WO1995012164A2 (en) 1993-10-29 1994-10-27 Frame buffer system designed for windowing operations

Publications (2)

Publication Number Publication Date
DE69432512D1 true DE69432512D1 (de) 2003-05-22
DE69432512T2 DE69432512T2 (de) 2004-04-22

Family

ID=22512623

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69432512T Expired - Fee Related DE69432512T2 (de) 1993-10-29 1994-10-27 Für fensterumgebungsoperationen entworfenes rasterpuffersystem

Country Status (6)

Country Link
US (1) US5528751A (de)
EP (1) EP0677190B1 (de)
JP (1) JPH08505255A (de)
KR (1) KR100335474B1 (de)
DE (1) DE69432512T2 (de)
WO (1) WO1995012164A2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5539430A (en) * 1993-10-29 1996-07-23 Sun Microsystems, Inc. Pipelined read write operations in a high speed frame buffer system
JPH08505244A (ja) * 1993-10-29 1996-06-04 サン・マイクロシステムズ・インコーポレーテッド ウィンドウ動作用に設計されたフレーム・バッファ・システムにおいてスクロール・レートを増大させる方法及び装置
US5764963A (en) * 1995-07-07 1998-06-09 Rambus, Inc. Method and apparatus for performing maskable multiple color block writes
US6230235B1 (en) 1996-08-08 2001-05-08 Apache Systems, Inc. Address lookup DRAM aging
US6104658A (en) * 1996-08-08 2000-08-15 Neomagic Corporation Distributed DRAM refreshing
US5781200A (en) * 1996-08-08 1998-07-14 Ulsi Systems Tile memory mapping for increased throughput in a dual bank access DRAM
KR100300972B1 (ko) * 1997-09-19 2001-09-03 윤종용 텍스춰매핑수행장치및텍스춰캐시의데이터억세스방법
US6542796B1 (en) * 2000-11-18 2003-04-01 Honeywell International Inc. Methods and apparatus for integrating, organizing, and accessing flight planning and other data on multifunction cockpit displays
TW514863B (en) * 2001-12-14 2002-12-21 Chi Mei Electronics Corp Overdrive system and method of liquid crystal display
CN100350448C (zh) * 2001-12-27 2007-11-21 奇美电子股份有限公司 液晶显示器的过载驱动系统与方法
US7313764B1 (en) * 2003-03-06 2007-12-25 Apple Inc. Method and apparatus to accelerate scrolling for buffered windows
CN1809869B (zh) 2003-06-30 2011-04-20 瑞萨电子株式会社 驱动器及其显示设备
US7573491B2 (en) * 2004-04-02 2009-08-11 David Hartkop Method for formatting images for angle-specific viewing in a scanning aperture display device
EP1622111A1 (de) * 2004-07-28 2006-02-01 Deutsche Thomson-Brandt Gmbh Leitungstreiberschaltung für Anzeigevorrichtung mit aktiver Matrix
JP4488042B2 (ja) * 2007-08-14 2010-06-23 セイコーエプソン株式会社 画像処理回路、表示装置及び印刷装置
JP4404116B2 (ja) 2007-08-14 2010-01-27 セイコーエプソン株式会社 画像処理回路、表示装置及び印刷装置
TWI416500B (zh) * 2009-12-28 2013-11-21 Inventec Besta Co Ltd 顯示系統及其加速顯示方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4648077A (en) * 1985-01-22 1987-03-03 Texas Instruments Incorporated Video serial accessed memory with midline load
US4769637A (en) * 1985-11-26 1988-09-06 Digital Equipment Corporation Video display control circuit arrangement
US5170157A (en) * 1986-05-20 1992-12-08 Takatoshi Ishii Memory device for an image display apparatus having a serial port and independently operable data registers
US5046023A (en) * 1987-10-06 1991-09-03 Hitachi, Ltd. Graphic processing system having bus connection control capable of high-speed parallel drawing processing in a frame buffer and a system memory
US4823302A (en) * 1987-01-30 1989-04-18 Rca Licensing Corporation Block oriented random access memory able to perform a data read, a data write and a data refresh operation in one block-access time
JPS63204595A (ja) * 1987-02-20 1988-08-24 Fujitsu Ltd マルチプレ−ンビデオｒａｍ構成方式
US4807189A (en) * 1987-08-05 1989-02-21 Texas Instruments Incorporated Read/write memory having a multiple column select mode
US5305078A (en) * 1992-01-21 1994-04-19 Exfo Electro-Optical Engineering Inc. Measurement of attenuation of optical fibers using transmitted wavelength and power information
US5282177A (en) * 1992-04-08 1994-01-25 Micron Technology, Inc. Multiple register block write method and circuit for video DRAMs

Also Published As

Publication number Publication date
EP0677190A4 (de) 1996-07-24
WO1995012164A2 (en) 1995-05-04
DE69432512T2 (de) 2004-04-22
KR100335474B1 (ko) 2002-09-26
WO1995012164A3 (en) 1995-05-26
US5528751A (en) 1996-06-18
KR950704741A (ko) 1995-11-20
EP0677190A1 (de) 1995-10-18
JPH08505255A (ja) 1996-06-04
EP0677190B1 (de) 2003-04-16

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Legal Events

Date Code Title Description
8332 No legal effect for de
8370 Indication of lapse of patent is to be deleted
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee