DE69500023D1 - Elektrisch veränderlicher Festspeicher mit Prüffunktionen - Google Patents

Elektrisch veränderlicher Festspeicher mit Prüffunktionen

Info

Publication number
DE69500023D1
DE69500023D1 DE69500023T DE69500023T DE69500023D1 DE 69500023 D1 DE69500023 D1 DE 69500023D1 DE 69500023 T DE69500023 T DE 69500023T DE 69500023 T DE69500023 T DE 69500023T DE 69500023 D1 DE69500023 D1 DE 69500023D1
Authority
DE
Germany
Prior art keywords
permanent memory
electrically variable
test functions
variable permanent
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69500023T
Other languages
English (en)
Other versions
DE69500023T2 (de
Inventor
Jean-Marie Gaultier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Publication of DE69500023D1 publication Critical patent/DE69500023D1/de
Application granted granted Critical
Publication of DE69500023T2 publication Critical patent/DE69500023T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/20—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic
DE69500023T 1994-04-08 1995-04-03 Elektrisch veränderlicher Festspeicher mit Prüffunktionen Expired - Fee Related DE69500023T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9404565A FR2718559B1 (fr) 1994-04-08 1994-04-08 Mémoire non volatile modifiable électriquement incorporant des fonctions de test.

Publications (2)

Publication Number Publication Date
DE69500023D1 true DE69500023D1 (de) 1996-09-26
DE69500023T2 DE69500023T2 (de) 1996-12-19

Family

ID=9462180

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69500023T Expired - Fee Related DE69500023T2 (de) 1994-04-08 1995-04-03 Elektrisch veränderlicher Festspeicher mit Prüffunktionen

Country Status (5)

Country Link
US (1) US5644530A (de)
EP (1) EP0676769B1 (de)
JP (1) JP2748335B2 (de)
DE (1) DE69500023T2 (de)
FR (1) FR2718559B1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69633000D1 (de) * 1996-03-29 2004-09-02 St Microelectronics Srl Zellendekodiererschaltkreis für einen nichtflüchtigen elektrisch programmierbaren Speicher und entsprechendes Verfahren
FR2771210B1 (fr) * 1997-11-18 2000-02-04 Sgs Thomson Microelectronics Procede de mise en oeuvre de la premiere programmation d'une memoire et memoire correspondante
US6141779A (en) * 1998-10-19 2000-10-31 Hewlett-Packard Company Method for automatically programming a redundancy map for a redundant circuit
US5999468A (en) * 1998-11-17 1999-12-07 Tanisys Technology, Inc. Method and system for identifying a memory module configuration
US6597609B2 (en) * 2001-08-30 2003-07-22 Micron Technology, Inc. Non-volatile memory with test rows for disturb detection
US7164613B2 (en) * 2004-11-19 2007-01-16 Infineon Technologies Ag Flexible internal address counting method and apparatus
US20070011596A1 (en) * 2005-06-22 2007-01-11 Jungwon Suh Parity check circuit to improve quality of memory device
KR100744013B1 (ko) 2006-07-31 2007-07-30 삼성전자주식회사 플래시 메모리 장치 및 그것의 소거 방법
US8997255B2 (en) * 2006-07-31 2015-03-31 Inside Secure Verifying data integrity in a data storage device
US7457155B2 (en) * 2006-08-31 2008-11-25 Micron Technology, Inc. Non-volatile memory device and method having bit-state assignments selected to minimize signal coupling

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4024386A (en) * 1974-11-19 1977-05-17 Texas Instruments Incorporated Electronic calculator or digital processor chip having test mode of operation
US4430735A (en) * 1981-05-26 1984-02-07 Burroughs Corporation Apparatus and technique for testing IC memories
US4672583A (en) * 1983-06-15 1987-06-09 Nec Corporation Dynamic random access memory device provided with test circuit for internal refresh circuit
JPS62120700A (ja) * 1985-11-20 1987-06-01 Fujitsu Ltd 半導体記憶装置
US4872168A (en) * 1986-10-02 1989-10-03 American Telephone And Telegraph Company, At&T Bell Laboratories Integrated circuit with memory self-test
JP3080743B2 (ja) * 1991-12-27 2000-08-28 日本電気株式会社 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
FR2718559B1 (fr) 1996-06-07
EP0676769B1 (de) 1996-08-21
EP0676769A1 (de) 1995-10-11
US5644530A (en) 1997-07-01
JPH07282600A (ja) 1995-10-27
JP2748335B2 (ja) 1998-05-06
FR2718559A1 (fr) 1995-10-13
DE69500023T2 (de) 1996-12-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee