DE69500157D1 - Signalverarbeitungsschaltung zur Durchführung des Viterbi Algorithmus - Google Patents

Signalverarbeitungsschaltung zur Durchführung des Viterbi Algorithmus

Info

Publication number
DE69500157D1
DE69500157D1 DE69500157T DE69500157T DE69500157D1 DE 69500157 D1 DE69500157 D1 DE 69500157D1 DE 69500157 T DE69500157 T DE 69500157T DE 69500157 T DE69500157 T DE 69500157T DE 69500157 D1 DE69500157 D1 DE 69500157D1
Authority
DE
Germany
Prior art keywords
implementing
signal processing
processing circuit
viterbi algorithm
viterbi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69500157T
Other languages
English (en)
Other versions
DE69500157T2 (de
Inventor
Michel Cartier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Application granted granted Critical
Publication of DE69500157D1 publication Critical patent/DE69500157D1/de
Publication of DE69500157T2 publication Critical patent/DE69500157T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3961—Arrangements of methods for branch or transition metric calculation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
    • H03M13/4169—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using traceback
DE69500157T 1994-09-05 1995-09-05 Signalverarbeitungsschaltung zur Durchführung des Viterbi Algorithmus Expired - Fee Related DE69500157T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9410620A FR2724273B1 (fr) 1994-09-05 1994-09-05 Circuit de traitement de signal pour mettre en oeuvre un algorithme de viterbi

Publications (2)

Publication Number Publication Date
DE69500157D1 true DE69500157D1 (de) 1997-03-27
DE69500157T2 DE69500157T2 (de) 1997-06-19

Family

ID=9466699

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69500157T Expired - Fee Related DE69500157T2 (de) 1994-09-05 1995-09-05 Signalverarbeitungsschaltung zur Durchführung des Viterbi Algorithmus

Country Status (5)

Country Link
US (1) US5881106A (de)
EP (1) EP0700164B1 (de)
JP (1) JPH08237144A (de)
DE (1) DE69500157T2 (de)
FR (1) FR2724273B1 (de)

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JP3338374B2 (ja) * 1997-06-30 2002-10-28 松下電器産業株式会社 演算処理方法および装置
US5987490A (en) * 1997-11-14 1999-11-16 Lucent Technologies Inc. Mac processor with efficient Viterbi ACS operation and automatic traceback store
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US6999521B1 (en) * 1999-12-23 2006-02-14 Lucent Technologies Inc. Method and apparatus for shortening the critical path of reduced complexity sequence estimation techniques
US6931072B2 (en) * 2000-04-06 2005-08-16 Lucent Technologies Inc. Upstream data transmission
EP1158683A1 (de) * 2000-05-24 2001-11-28 Infineon Technologies AG Vorrichtung und Verfahren zum Durchführen eines Viterbi-Algorithmus
US7020214B2 (en) * 2000-09-18 2006-03-28 Lucent Technologies Inc. Method and apparatus for path metric processing in telecommunications systems
DE10064102A1 (de) * 2000-12-21 2002-07-25 Infineon Technologies Ag Architektur für DSP, Entzerrer und Kanaldekodierer
US7249242B2 (en) * 2002-10-28 2007-07-24 Nvidia Corporation Input pipeline registers for a node in an adaptive computing engine
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US7489779B2 (en) * 2001-03-22 2009-02-10 Qstholdings, Llc Hardware implementation of the secure hash standard
US7752419B1 (en) 2001-03-22 2010-07-06 Qst Holdings, Llc Method and system for managing hardware resources to implement system functions using an adaptive computing architecture
US7653710B2 (en) 2002-06-25 2010-01-26 Qst Holdings, Llc. Hardware task manager
US7962716B2 (en) 2001-03-22 2011-06-14 Qst Holdings, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US7400668B2 (en) * 2001-03-22 2008-07-15 Qst Holdings, Llc Method and system for implementing a system acquisition function for use with a communication device
US7656959B2 (en) 2001-04-13 2010-02-02 Agere Systems Inc. Pipelined decision-feedback unit in a reduced-state viterbi detector with local feedback
US20050264906A1 (en) * 2004-05-25 2005-12-01 Haratsch Erich F Method and apparatus for reduced-state Viterbi detection in a read channel of a magnetic recording system
US6577678B2 (en) 2001-05-08 2003-06-10 Quicksilver Technology Method and system for reconfigurable channel coding
US20020184291A1 (en) * 2001-05-31 2002-12-05 Hogenauer Eugene B. Method and system for scheduling in an adaptable computing engine
US6476739B1 (en) * 2001-09-18 2002-11-05 The Aerospace Corporation Method and processing system for estimating likelihood ratios for input symbol values
AU2002357739A1 (en) * 2001-11-16 2003-06-10 Morpho Technologies Viterbi convolutional coding method and apparatus
US7046635B2 (en) * 2001-11-28 2006-05-16 Quicksilver Technology, Inc. System for authorizing functionality in adaptable hardware devices
US6986021B2 (en) 2001-11-30 2006-01-10 Quick Silver Technology, Inc. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
US8412915B2 (en) * 2001-11-30 2013-04-02 Altera Corporation Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements
US7215701B2 (en) * 2001-12-12 2007-05-08 Sharad Sambhwani Low I/O bandwidth method and system for implementing detection and identification of scrambling codes
US7231508B2 (en) * 2001-12-13 2007-06-12 Quicksilver Technologies Configurable finite state machine for operation of microinstruction providing execution enable control value
US7403981B2 (en) * 2002-01-04 2008-07-22 Quicksilver Technology, Inc. Apparatus and method for adaptive multimedia reception and transmission in communication environments
US6928605B2 (en) * 2002-03-29 2005-08-09 Intel Corporation Add-compare-select accelerator using pre-compare-select-add operation
US7289569B2 (en) * 2002-04-16 2007-10-30 Thomson Licensing HDTV trellis decoder architecture
US7660984B1 (en) 2003-05-13 2010-02-09 Quicksilver Technology Method and system for achieving individualized protected space in an operating system
US7328414B1 (en) 2003-05-13 2008-02-05 Qst Holdings, Llc Method and system for creating and programming an adaptive computing engine
US8108656B2 (en) 2002-08-29 2012-01-31 Qst Holdings, Llc Task definition for specifying resource requirements
WO2004034227A2 (en) * 2002-10-11 2004-04-22 Quicksilver Technology, Inc. Reconfigurable bit-manipulation node
US7937591B1 (en) 2002-10-25 2011-05-03 Qst Holdings, Llc Method and system for providing a device which can be adapted on an ongoing basis
US8276135B2 (en) 2002-11-07 2012-09-25 Qst Holdings Llc Profiling of software and circuit designs utilizing data operation analyses
US7225301B2 (en) 2002-11-22 2007-05-29 Quicksilver Technologies External memory controller node
US7200837B2 (en) * 2003-08-21 2007-04-03 Qst Holdings, Llc System, method and software for static and dynamic programming and configuration of an adaptive computing architecture
US6864812B1 (en) * 2004-02-05 2005-03-08 Broadcom Corporation Hardware efficient implementation of finite impulse response filters with limited range input signals
US7653154B2 (en) * 2004-05-25 2010-01-26 Agere Systems Inc. Method and apparatus for precomputation and pipelined selection of intersymbol interference estimates in a reduced-state Viterbi detector
US7380199B2 (en) * 2004-05-25 2008-05-27 Agere Systems Inc. Method and apparatus for precomputation and pipelined selection of branch metrics in a reduced-state Viterbi detector
US7487432B2 (en) * 2004-05-25 2009-02-03 Agere Systems Inc. Method and apparatus for multiple step Viterbi detection with local feedback
US20060068911A1 (en) * 2004-09-30 2006-03-30 Microsoft Corporation Game console communication with a computer
US7275204B2 (en) * 2004-09-30 2007-09-25 Marvell International Ltd. Distributed ring control circuits for Viterbi traceback
JP5990466B2 (ja) 2010-01-21 2016-09-14 スビラル・インコーポレーテッド ストリームに基づく演算を実装するための汎用複数コアシステムのための方法および装置

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DE3910739C3 (de) * 1989-04-03 1996-11-21 Deutsche Forsch Luft Raumfahrt Verfahren zum Verallgemeinern des Viterbi-Algorithmus und Einrichtungen zur Durchführung des Verfahrens
US5027374A (en) * 1990-03-26 1991-06-25 Motorola, Inc. Bit serial Viterbi decoder add/compare/select array
US5220570A (en) * 1990-11-30 1993-06-15 The Board Of Trustees Of The Leland Stanford Junior University Programmable viterbi signal processor
JP2710464B2 (ja) * 1990-11-30 1998-02-10 日本オーチス・エレベータ株式会社 電磁ブレーキ
US5291499A (en) * 1992-03-16 1994-03-01 Cirrus Logic, Inc. Method and apparatus for reduced-complexity viterbi-type sequence detectors
JP3348303B2 (ja) * 1993-02-05 2002-11-20 ソニー株式会社 ビタビ復号方法およびその装置
US5454014A (en) * 1993-11-16 1995-09-26 At&T Corp. Digital signal processor
US5432804A (en) * 1993-11-16 1995-07-11 At&T Corp. Digital processor and viterbi decoder having shared memory
US5513220A (en) * 1993-11-16 1996-04-30 At&T Corp. Digital receiver with minimum cost index register
TW243568B (en) * 1993-11-16 1995-03-21 At & T Corp Digital signal processor with an embedded viterbi co-processor
EP0656712A1 (de) * 1993-11-16 1995-06-07 AT&T Corp. Viterbi-Entzerrer mit "Traceback" variabler länge
US5490178A (en) * 1993-11-16 1996-02-06 At&T Corp. Power and time saving initial tracebacks
US5465275A (en) * 1993-11-16 1995-11-07 At&T Ipm Corp. Efficient utilization of present state/next state registers
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US5550870A (en) * 1994-03-02 1996-08-27 Lucent Technologies Inc. Viterbi processor

Also Published As

Publication number Publication date
JPH08237144A (ja) 1996-09-13
EP0700164A1 (de) 1996-03-06
FR2724273B1 (fr) 1997-01-03
EP0700164B1 (de) 1997-02-12
DE69500157T2 (de) 1997-06-19
US5881106A (en) 1999-03-09
FR2724273A1 (fr) 1996-03-08

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee