DE69518676D1 - Cache-Speicheranordnung für einen Speicher - Google Patents

Cache-Speicheranordnung für einen Speicher

Info

Publication number
DE69518676D1
DE69518676D1 DE69518676T DE69518676T DE69518676D1 DE 69518676 D1 DE69518676 D1 DE 69518676D1 DE 69518676 T DE69518676 T DE 69518676T DE 69518676 T DE69518676 T DE 69518676T DE 69518676 D1 DE69518676 D1 DE 69518676D1
Authority
DE
Germany
Prior art keywords
memory
arrangement
cache
cache memory
memory arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69518676T
Other languages
English (en)
Other versions
DE69518676T2 (de
Inventor
Gordon Kurpanek
Eric Delano
Michael A Buckley
William R Bryg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE69518676D1 publication Critical patent/DE69518676D1/de
Publication of DE69518676T2 publication Critical patent/DE69518676T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
DE69518676T 1994-02-14 1995-02-03 Cache-Speicheranordnung für einen Speicher Expired - Lifetime DE69518676T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/196,042 US5603004A (en) 1994-02-14 1994-02-14 Method for decreasing time penalty resulting from a cache miss in a multi-level cache system

Publications (2)

Publication Number Publication Date
DE69518676D1 true DE69518676D1 (de) 2000-10-12
DE69518676T2 DE69518676T2 (de) 2001-01-04

Family

ID=22723904

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69518676T Expired - Lifetime DE69518676T2 (de) 1994-02-14 1995-02-03 Cache-Speicheranordnung für einen Speicher

Country Status (4)

Country Link
US (1) US5603004A (de)
EP (1) EP0667580B1 (de)
JP (1) JP3618385B2 (de)
DE (1) DE69518676T2 (de)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6021471A (en) * 1994-11-15 2000-02-01 Advanced Micro Devices, Inc. Multiple level cache control system with address and data pipelines
US5897654A (en) * 1995-02-10 1999-04-27 International Business Machines Corporation Method and system for efficiently fetching from cache during a cache fill operation
US5732242A (en) 1995-03-24 1998-03-24 Silicon Graphics, Inc. Consistently specifying way destinations through prefetching hints
EP0752645B1 (de) * 1995-07-07 2017-11-22 Oracle America, Inc. Abstimmbare Softwaresteuerung von Pufferspeichern einer Harvard-Architektur mittels Vorausladebefehlen
US5860095A (en) * 1996-01-02 1999-01-12 Hewlett-Packard Company Conflict cache having cache miscounters for a computer memory system
US5835946A (en) * 1996-04-18 1998-11-10 International Business Machines Corporation High performance implementation of the load reserve instruction in a superscalar microprocessor that supports multi-level cache organizations
US5761468A (en) * 1996-05-15 1998-06-02 Sun Microsystems Inc Hardware mechanism for optimizing instruction and data prefetching by forming augmented prefetch instructions
JP3068469B2 (ja) 1996-08-28 2000-07-24 新潟日本電気株式会社 ２次レベルキャッシュメモリシステム
US5954812A (en) * 1996-10-29 1999-09-21 Texas Instruments Incorporated Apparatus for caching system management memory in a computer having a system management mode employing address translation
US5752261A (en) * 1996-11-07 1998-05-12 Ncr Corporation Method and apparatus for detecting thrashing in a cache memory
US6223256B1 (en) 1997-07-22 2001-04-24 Hewlett-Packard Company Computer cache memory with classes and dynamic selection of replacement algorithms
US5909697A (en) * 1997-09-30 1999-06-01 Sun Microsystems, Inc. Reducing cache misses by snarfing writebacks in non-inclusive memory systems
US6073212A (en) * 1997-09-30 2000-06-06 Sun Microsystems, Inc. Reducing bandwidth and areas needed for non-inclusive memory hierarchy by using dual tags
US6549930B1 (en) 1997-11-26 2003-04-15 Compaq Computer Corporation Method for scheduling threads in a multithreaded processor
US6175814B1 (en) 1997-11-26 2001-01-16 Compaq Computer Corporation Apparatus for determining the instantaneous average number of instructions processed
US6332178B1 (en) 1997-11-26 2001-12-18 Compaq Computer Corporation Method for estimating statistics of properties of memory system transactions
US6195748B1 (en) 1997-11-26 2001-02-27 Compaq Computer Corporation Apparatus for sampling instruction execution information in a processor pipeline
US6374367B1 (en) 1997-11-26 2002-04-16 Compaq Computer Corporation Apparatus and method for monitoring a computer system to guide optimization
US6237059B1 (en) 1997-11-26 2001-05-22 Compaq Computer Corporation Method for estimating statistics of properties of memory system interactions among contexts in a computer system
US6163840A (en) * 1997-11-26 2000-12-19 Compaq Computer Corporation Method and apparatus for sampling multiple potentially concurrent instructions in a processor pipeline
US6442585B1 (en) 1997-11-26 2002-08-27 Compaq Computer Corporation Method for scheduling contexts based on statistics of memory system interactions in a computer system
US6202127B1 (en) * 1997-11-26 2001-03-13 Compaq Computer Corporation Apparatus for spatial and temporal sampling in a computer memory system
US6237073B1 (en) 1997-11-26 2001-05-22 Compaq Computer Corporation Method for providing virtual memory to physical memory page mapping in a computer operating system that randomly samples state information
US6253291B1 (en) 1998-02-13 2001-06-26 Sun Microsystems, Inc. Method and apparatus for relaxing the FIFO ordering constraint for memory accesses in a multi-processor asynchronous cache system
US6253301B1 (en) * 1998-04-16 2001-06-26 Compaq Computer Corporation Method and apparatus for a dedicated physically indexed copy of the data cache tag arrays
US6253285B1 (en) * 1998-04-16 2001-06-26 Compaq Computer Corporation Method and apparatus for minimizing dcache index match aliasing using hashing in synonym/subset processing
US6397296B1 (en) * 1999-02-19 2002-05-28 Hitachi Ltd. Two-level instruction cache for embedded processors
JP4341186B2 (ja) 2001-01-22 2009-10-07 株式会社日立製作所 メモリシステム
US6904498B2 (en) * 2002-10-08 2005-06-07 Netcell Corp. Raid controller disk write mask
US7203798B2 (en) * 2003-03-20 2007-04-10 Matsushita Electric Industrial Co., Ltd. Data memory cache unit and data memory cache system
US7143239B2 (en) * 2003-08-07 2006-11-28 Hewlett-Packard Development Company, L.P. Cache structure and methodology
US7937691B2 (en) 2003-09-30 2011-05-03 International Business Machines Corporation Method and apparatus for counting execution of specific instructions and accesses to specific data locations
US7395527B2 (en) 2003-09-30 2008-07-01 International Business Machines Corporation Method and apparatus for counting instruction execution and data accesses
US7373637B2 (en) * 2003-09-30 2008-05-13 International Business Machines Corporation Method and apparatus for counting instruction and memory location ranges
US7421681B2 (en) * 2003-10-09 2008-09-02 International Business Machines Corporation Method and system for autonomic monitoring of semaphore operation in an application
US8381037B2 (en) * 2003-10-09 2013-02-19 International Business Machines Corporation Method and system for autonomic execution path selection in an application
US7392370B2 (en) 2004-01-14 2008-06-24 International Business Machines Corporation Method and apparatus for autonomically initiating measurement of secondary metrics based on hardware counter values for primary metrics
US7526757B2 (en) * 2004-01-14 2009-04-28 International Business Machines Corporation Method and apparatus for maintaining performance monitoring structures in a page table for use in monitoring performance of a computer program
US7895382B2 (en) * 2004-01-14 2011-02-22 International Business Machines Corporation Method and apparatus for qualifying collection of performance monitoring events by types of interrupt when interrupt occurs
US7496908B2 (en) * 2004-01-14 2009-02-24 International Business Machines Corporation Method and apparatus for optimizing code execution using annotated trace information having performance indicator and counter information
US7415705B2 (en) * 2004-01-14 2008-08-19 International Business Machines Corporation Autonomic method and apparatus for hardware assist for patching code
US8135915B2 (en) * 2004-03-22 2012-03-13 International Business Machines Corporation Method and apparatus for hardware assistance for prefetching a pointer to a data structure identified by a prefetch indicator
US7421684B2 (en) 2004-03-22 2008-09-02 International Business Machines Corporation Method and apparatus for autonomic test case feedback using hardware assistance for data coverage
US7526616B2 (en) * 2004-03-22 2009-04-28 International Business Machines Corporation Method and apparatus for prefetching data from a data structure
JP4691335B2 (ja) * 2004-07-30 2011-06-01 富士通株式会社 記憶制御装置、中央処理装置、情報処理装置及び記憶制御装置の制御方法
US7373480B2 (en) * 2004-11-18 2008-05-13 Sun Microsystems, Inc. Apparatus and method for determining stack distance of running software for estimating cache miss rates based upon contents of a hash table
US7366871B2 (en) * 2004-11-18 2008-04-29 Sun Microsystems, Inc. Apparatus and method for determining stack distance including spatial locality of running software for estimating cache miss rates based upon contents of a hash table
US7386669B2 (en) * 2005-03-31 2008-06-10 International Business Machines Corporation System and method of improving task switching and page translation performance utilizing a multilevel translation lookaside buffer
US7409502B2 (en) * 2006-05-11 2008-08-05 Freescale Semiconductor, Inc. Selective cache line allocation instruction execution and circuitry
JP4491500B2 (ja) * 2007-01-30 2010-06-30 富士通株式会社 演算処理装置、情報処理装置及び演算処理装置の制御方法
JP2009053820A (ja) * 2007-08-24 2009-03-12 Nec Electronics Corp 階層型キャッシュメモリシステム
US8478942B2 (en) * 2010-09-27 2013-07-02 Advanced Micro Devices, Inc. Method and apparatus for reducing processor cache pollution caused by aggressive prefetching
CN104169892A (zh) * 2012-03-28 2014-11-26 华为技术有限公司 并发访问的组相联溢出缓存
US9652233B2 (en) * 2013-08-20 2017-05-16 Apple Inc. Hint values for use with an operand cache
US9489149B2 (en) * 2014-06-16 2016-11-08 Netapp, Inc. Methods and systems for using a write cache in a storage system
WO2016009247A1 (en) * 2014-07-14 2016-01-21 Via Alliance Semiconductor Co., Ltd. Cache system with primary cache and overflow cache that use different indexing schemes
US9558127B2 (en) * 2014-09-09 2017-01-31 Intel Corporation Instruction and logic for a cache prefetcher and dataless fill buffer
CN105814549B (zh) * 2014-10-08 2019-03-01 上海兆芯集成电路有限公司 具有主高速缓存器和溢出fifo高速缓存器的高速缓存器系统
US20170046278A1 (en) * 2015-08-14 2017-02-16 Qualcomm Incorporated Method and apparatus for updating replacement policy information for a fully associative buffer cache

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4774654A (en) * 1984-12-24 1988-09-27 International Business Machines Corporation Apparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depending upon state of replacing bit in the low speed memory
US4928239A (en) * 1986-06-27 1990-05-22 Hewlett-Packard Company Cache memory with variable fetch and replacement schemes
US5058006A (en) * 1988-06-27 1991-10-15 Digital Equipment Corporation Method and apparatus for filtering invalidate requests
US5146578A (en) * 1989-05-01 1992-09-08 Zenith Data Systems Corporation Method of varying the amount of data prefetched to a cache memory in dependence on the history of data requests
US5307477A (en) * 1989-12-01 1994-04-26 Mips Computer Systems, Inc. Two-level cache memory system
IT1238313B (it) * 1990-01-18 1993-07-12 Memoria tampone in tandem
US5163140A (en) * 1990-02-26 1992-11-10 Nexgen Microsystems Two-level branch prediction cache
EP0449540B1 (de) * 1990-03-27 2000-05-17 Digital Equipment Corporation Speicher-Anordnung und Verfahren mit Vorausholungspuffer
US5317718A (en) * 1990-03-27 1994-05-31 Digital Equipment Corporation Data processing system and method with prefetch buffers
US5261066A (en) * 1990-03-27 1993-11-09 Digital Equipment Corporation Data processing system and method with small fully-associative cache and prefetch buffers
CA2044689A1 (en) * 1990-06-15 1991-12-16 Roger E. Tipley Multilevel inclusion in multilevel cache hierarchies
JPH0612323A (ja) * 1992-02-27 1994-01-21 Hewlett Packard Co <Hp> キャッシュメモリシステム

Also Published As

Publication number Publication date
DE69518676T2 (de) 2001-01-04
EP0667580A2 (de) 1995-08-16
EP0667580B1 (de) 2000-09-06
EP0667580A3 (de) 1996-07-31
JPH07253926A (ja) 1995-10-03
JP3618385B2 (ja) 2005-02-09
US5603004A (en) 1997-02-11

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE),

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE