DE69526895D1 - Verfahren zur Herstellung einer halbleitenden Anordnung und einer Halbleiterscheibe - Google Patents

Verfahren zur Herstellung einer halbleitenden Anordnung und einer Halbleiterscheibe

Info

Publication number
DE69526895D1
DE69526895D1 DE69526895T DE69526895T DE69526895D1 DE 69526895 D1 DE69526895 D1 DE 69526895D1 DE 69526895 T DE69526895 T DE 69526895T DE 69526895 T DE69526895 T DE 69526895T DE 69526895 D1 DE69526895 D1 DE 69526895D1
Authority
DE
Germany
Prior art keywords
producing
semiconductor wafer
semiconducting device
semiconducting
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69526895T
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English (en)
Other versions
DE69526895T2 (de
Inventor
Keiichiro Kata
Shinichi Chikaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=17018517&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69526895(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69526895D1 publication Critical patent/DE69526895D1/de
Publication of DE69526895T2 publication Critical patent/DE69526895T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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DE69526895T 1994-09-30 1995-10-02 Verfahren zur Herstellung einer halbleitenden Anordnung und einer Halbleiterscheibe Expired - Fee Related DE69526895T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6237653A JP2792532B2 (ja) 1994-09-30 1994-09-30 半導体装置の製造方法及び半導体ウエハー

Publications (2)

Publication Number Publication Date
DE69526895D1 true DE69526895D1 (de) 2002-07-11
DE69526895T2 DE69526895T2 (de) 2003-02-27

Family

ID=17018517

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69526895T Expired - Fee Related DE69526895T2 (de) 1994-09-30 1995-10-02 Verfahren zur Herstellung einer halbleitenden Anordnung und einer Halbleiterscheibe

Country Status (6)

Country Link
US (2) US5844304A (de)
EP (1) EP0704895B1 (de)
JP (1) JP2792532B2 (de)
KR (1) KR100241573B1 (de)
CA (1) CA2159242C (de)
DE (1) DE69526895T2 (de)

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JP2792532B2 (ja) * 1994-09-30 1998-09-03 日本電気株式会社 半導体装置の製造方法及び半導体ウエハー
US6111317A (en) * 1996-01-18 2000-08-29 Kabushiki Kaisha Toshiba Flip-chip connection type semiconductor integrated circuit device
EP0821407A3 (de) * 1996-02-23 1998-03-04 Matsushita Electric Industrial Co., Ltd. Halbleitervorrichtungen mit herausragenden Kontakten und Herstellungsverfahren
US6169329B1 (en) 1996-04-02 2001-01-02 Micron Technology, Inc. Semiconductor devices having interconnections using standardized bonding locations and methods of designing
DE19613561C2 (de) * 1996-04-04 2002-04-11 Micronas Gmbh Verfahren zum Vereinzeln von in einem Körper miteinander verbundenen, elektrisch getesteten elektronischen Elementen
ES2288760T3 (es) 1996-04-25 2008-01-16 Bioarray Solutions Ltd. Ensamblaje electrocinetico controlado por luz de particulas proximas a superficies.
KR100186333B1 (ko) * 1996-06-20 1999-03-20 문정환 칩 사이즈 반도체 패키지 및 그 제조방법
US6075279A (en) * 1996-06-26 2000-06-13 Sanyo Electric Co., Ltd. Semiconductor device
TW571373B (en) 1996-12-04 2004-01-11 Seiko Epson Corp Semiconductor device, circuit substrate, and electronic machine
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JP3796016B2 (ja) 1997-03-28 2006-07-12 三洋電機株式会社 半導体装置
JP2962351B2 (ja) * 1997-03-31 1999-10-12 日本電気株式会社 半導体チップへの接合構造及びそれを用いた半導体装置
JP3335575B2 (ja) 1997-06-06 2002-10-21 松下電器産業株式会社 半導体装置およびその製造方法
US6034437A (en) * 1997-06-06 2000-03-07 Rohm Co., Ltd. Semiconductor device having a matrix of bonding pads
US6441473B1 (en) * 1997-09-12 2002-08-27 Agere Systems Guardian Corp. Flip chip semiconductor device
JP3068534B2 (ja) * 1997-10-14 2000-07-24 九州日本電気株式会社 半導体装置
KR20010031602A (ko) * 1997-10-30 2001-04-16 가나이 쓰토무 반도체 장치 및 그 제조 방법
TW434646B (en) 1997-11-21 2001-05-16 Rohm Co Ltd Semiconductor device and method for making the same
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USRE39603E1 (en) 2007-05-01
KR100241573B1 (ko) 2000-02-01
DE69526895T2 (de) 2003-02-27
EP0704895A2 (de) 1996-04-03
EP0704895A3 (de) 1996-12-04
EP0704895B1 (de) 2002-06-05
JP2792532B2 (ja) 1998-09-03
US5844304A (en) 1998-12-01

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