DE69613723D1 - Verfahren zur Herstellung einer Halbleiteranordnung mit einem Kondensator - Google Patents

Verfahren zur Herstellung einer Halbleiteranordnung mit einem Kondensator

Info

Publication number
DE69613723D1
DE69613723D1 DE69613723T DE69613723T DE69613723D1 DE 69613723 D1 DE69613723 D1 DE 69613723D1 DE 69613723 T DE69613723 T DE 69613723T DE 69613723 T DE69613723 T DE 69613723T DE 69613723 D1 DE69613723 D1 DE 69613723D1
Authority
DE
Germany
Prior art keywords
capacitor
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69613723T
Other languages
English (en)
Other versions
DE69613723T2 (de
Inventor
Yoshihisa Nagano
Eiji Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Application granted granted Critical
Publication of DE69613723D1 publication Critical patent/DE69613723D1/de
Publication of DE69613723T2 publication Critical patent/DE69613723T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
DE69613723T 1995-02-03 1996-01-27 Verfahren zur Herstellung einer Halbleiteranordnung mit einem Kondensator Expired - Lifetime DE69613723T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7016829A JP2953974B2 (ja) 1995-02-03 1995-02-03 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69613723D1 true DE69613723D1 (de) 2001-08-16
DE69613723T2 DE69613723T2 (de) 2002-04-25

Family

ID=11927088

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69613723T Expired - Lifetime DE69613723T2 (de) 1995-02-03 1996-01-27 Verfahren zur Herstellung einer Halbleiteranordnung mit einem Kondensator
DE69628677T Expired - Lifetime DE69628677T2 (de) 1995-02-03 1996-01-27 Ätzen einer Platinelektrode und eine dielektrische oder ferroelektrische Schicht

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE69628677T Expired - Lifetime DE69628677T2 (de) 1995-02-03 1996-01-27 Ätzen einer Platinelektrode und eine dielektrische oder ferroelektrische Schicht

Country Status (6)

Country Link
US (1) US5652171A (de)
EP (2) EP0725430B1 (de)
JP (1) JP2953974B2 (de)
KR (1) KR0185489B1 (de)
CN (1) CN1080926C (de)
DE (2) DE69613723T2 (de)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09251983A (ja) * 1996-03-15 1997-09-22 Rohm Co Ltd ドライエッチング方法
DE19646208C2 (de) * 1996-11-08 2001-08-30 Infineon Technologies Ag Verfahren zur Herstellung eines Kondensators und Speicherfeld
KR19980060614A (ko) * 1996-12-31 1998-10-07 김영환 반도체 소자의 제조방법
JP3024747B2 (ja) * 1997-03-05 2000-03-21 日本電気株式会社 半導体メモリの製造方法
EP0865079A3 (de) 1997-03-13 1999-10-20 Applied Materials, Inc. Verfahren zur Beseitigung von auf geätzten Platinflächen abgelagerten Verunreinigungen
DE19712540C1 (de) * 1997-03-25 1998-08-13 Siemens Ag Herstellverfahren für eine Kondensatorelektrode aus einem Platinmetall
US5846884A (en) * 1997-06-20 1998-12-08 Siemens Aktiengesellschaft Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing
KR100458293B1 (ko) * 1997-12-20 2005-02-05 주식회사 하이닉스반도체 반도체소자의금속배선후처리방법
US6265318B1 (en) 1998-01-13 2001-07-24 Applied Materials, Inc. Iridium etchant methods for anisotropic profile
US6323132B1 (en) 1998-01-13 2001-11-27 Applied Materials, Inc. Etching methods for anisotropic platinum profile
US6919168B2 (en) 1998-01-13 2005-07-19 Applied Materials, Inc. Masking methods and etching sequences for patterning electrodes of high density RAM capacitors
WO1999036956A1 (en) 1998-01-13 1999-07-22 Applied Materials, Inc. Etching methods for anisotropic platinum profile
KR100333127B1 (ko) * 1998-06-29 2002-09-05 주식회사 하이닉스반도체 반도체소자의캐패시터제조방법
US6204172B1 (en) 1998-09-03 2001-03-20 Micron Technology, Inc. Low temperature deposition of barrier layers
US6323081B1 (en) 1998-09-03 2001-11-27 Micron Technology, Inc. Diffusion barrier layers and methods of forming same
US7060584B1 (en) * 1999-07-12 2006-06-13 Zilog, Inc. Process to improve high performance capacitor properties in integrated MOS technology
US6458648B1 (en) * 1999-12-17 2002-10-01 Agere Systems Guardian Corp. Method for in-situ removal of side walls in MOM capacitor formation
KR100358149B1 (ko) * 2000-06-30 2002-10-25 주식회사 하이닉스반도체 플라즈마 처리를 이용하여 강유전체 캐패시터의 열화를회복시키는 강유전체 메모리 소자 제조 방법
US20020123008A1 (en) 2000-12-21 2002-09-05 Ning Xiang J. Isotropic etch to form MIM capacitor top plates
US6444479B1 (en) * 2001-04-18 2002-09-03 Hynix Semiconductor Inc. Method for forming capacitor of semiconductor device
JP4032916B2 (ja) * 2001-11-28 2008-01-16 三菱化学株式会社 エッチング液
EP1321977A1 (de) * 2001-12-17 2003-06-25 AMI Semiconductor Belgium BVBA Verfahren zur Reduzierung von elektrischen Ladungen erzeugt durch einen vorherigen Prozessschritt auf einer leitenden Struktur
JP4865978B2 (ja) * 2002-02-28 2012-02-01 富士通セミコンダクター株式会社 半導体装置の製造方法
JP2003257942A (ja) * 2002-02-28 2003-09-12 Fujitsu Ltd 半導体装置の製造方法
JP4085094B2 (ja) * 2004-02-19 2008-04-30 シャープ株式会社 導電素子基板の製造方法、液晶表示装置の製造方法
US7071117B2 (en) * 2004-02-27 2006-07-04 Micron Technology, Inc. Semiconductor devices and methods for depositing a dielectric film
JP2006313833A (ja) * 2005-05-09 2006-11-16 Seiko Epson Corp 強誘電体キャパシタの形成方法、強誘電体キャパシタおよび電子デバイス
US20060278339A1 (en) * 2005-06-13 2006-12-14 Lam Research Corporation, A Delaware Corporation Etch rate uniformity using the independent movement of electrode pieces
JP2009266952A (ja) * 2008-04-23 2009-11-12 Seiko Epson Corp デバイスの製造方法及び製造装置
JP2011119779A (ja) * 2011-03-22 2011-06-16 Seiko Epson Corp 強誘電体キャパシタの形成方法、強誘電体キャパシタおよび電子デバイス
CN102956430A (zh) * 2012-05-25 2013-03-06 深圳市华星光电技术有限公司 取代膜层上氯原子的方法
US9224592B2 (en) * 2013-09-12 2015-12-29 Texas Intruments Incorporated Method of etching ferroelectric capacitor stack
JP6210039B2 (ja) * 2014-09-24 2017-10-11 セントラル硝子株式会社 付着物の除去方法及びドライエッチング方法
JP7199174B2 (ja) * 2018-07-26 2023-01-05 東京エレクトロン株式会社 エッチング方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4325984B2 (en) * 1980-07-28 1998-03-03 Fairchild Camera & Inst Plasma passivation technique for the prevention of post-etch corrosion of plasma-etched aluminum films
JPS593927A (ja) * 1982-06-29 1984-01-10 Fujitsu Ltd 薄膜のエツチング方法
JPS59189633A (ja) * 1983-04-13 1984-10-27 Fujitsu Ltd 半導体装置の製造方法
JPS61160939A (ja) * 1985-01-09 1986-07-21 Nec Corp ドライエツチング後Ｓｉ表面損傷の乾式による除去方法
US4666555A (en) * 1985-08-23 1987-05-19 Intel Corporation Plasma etching of silicon using fluorinated gas mixtures
US4847212A (en) * 1987-01-12 1989-07-11 Itt Gallium Arsenide Technology Center Self-aligned gate FET process using undercut etch mask
JPH02151031A (ja) * 1988-12-02 1990-06-11 Hitachi Ltd 半導体装置の製造方法
JPH03155621A (ja) * 1989-07-12 1991-07-03 Toshiba Corp ドライエッチング方法
US5316572A (en) * 1989-12-11 1994-05-31 Nmb Ltd. Method of manufacturing concrete for placement in air not requiring consolidation
DE69132811T2 (de) * 1990-06-27 2002-04-04 Fujitsu Ltd Verfahren zum herstellen eines integrierten halbleiterschaltkreises
JPH0467636A (ja) * 1990-07-06 1992-03-03 Mitsubishi Electric Corp 半導体装置の製造方法
US5216572A (en) * 1992-03-19 1993-06-01 Ramtron International Corporation Structure and method for increasing the dielectric constant of integrated ferroelectric capacitors
JPH0649667A (ja) * 1992-07-30 1994-02-22 Sharp Corp ドライエッチング方法及びその装置
US5335138A (en) * 1993-02-12 1994-08-02 Micron Semiconductor, Inc. High dielectric constant capacitor and method of manufacture
JP3460347B2 (ja) * 1994-03-30 2003-10-27 松下電器産業株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0932192A1 (de) 1999-07-28
CN1080926C (zh) 2002-03-13
CN1136218A (zh) 1996-11-20
DE69613723T2 (de) 2002-04-25
JPH08213364A (ja) 1996-08-20
JP2953974B2 (ja) 1999-09-27
EP0725430B1 (de) 2001-07-11
EP0725430A3 (de) 1998-05-27
EP0725430A2 (de) 1996-08-07
KR0185489B1 (ko) 1999-04-15
DE69628677T2 (de) 2004-05-13
EP0932192B1 (de) 2003-06-11
US5652171A (en) 1997-07-29
DE69628677D1 (de) 2003-07-17

Similar Documents

Publication Publication Date Title
DE69613723T2 (de) Verfahren zur Herstellung einer Halbleiteranordnung mit einem Kondensator
DE69317800T2 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE69427176D1 (de) Verfahren zur Herstellung einer Halbleiter-Kondensator-Elektrode
DE69330980T2 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE69421592T2 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE69232432T2 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE69231803D1 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE69617854D1 (de) Verfahren zur Herstellung einer photovoltaischen Vorrichtung
DE69032773T2 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE68929150D1 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE69503532D1 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE69627215T2 (de) Verfahren zur Herstellung eines Halbleiterbauelements
DE69633367D1 (de) Verfahren zur Herstellung eines in einer Halbleitervorrichtung integrierten Kondensators
DE69323979T2 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE69636404D1 (de) Verfahren zur Herstellung einer photoelektrischen Umwandlungsvorrichtung
DE59608481D1 (de) Verfahren zur Herstellung einer Halbleiteranordnung mit Kondensator
DE69030709D1 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE69523576D1 (de) Verfahren zur Herstellung einer Halbleiteranordnung mit selbstjustiertem Polycid
DE69031702T2 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE69416808D1 (de) Verfahren zur Herstellung einer mehrschichtigen Halbleitervorrichtung
DE69615642D1 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE69326908D1 (de) Verfahren zur Herstellung einer Halbleiter-Anordnung
DE69031153T2 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE69522413T2 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE69024859T2 (de) Verfahren zur Herstellung einer Halbleitervorrichtung

Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO. LTD., OSAKA, JP

8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP