DE69615538T2 - Integrierte speicherredundanzschaltung für programmierbare festwertspeicher und progammierungsverfahren - Google Patents

Integrierte speicherredundanzschaltung für programmierbare festwertspeicher und progammierungsverfahren

Info

Publication number
DE69615538T2
DE69615538T2 DE69615538T DE69615538T DE69615538T2 DE 69615538 T2 DE69615538 T2 DE 69615538T2 DE 69615538 T DE69615538 T DE 69615538T DE 69615538 T DE69615538 T DE 69615538T DE 69615538 T2 DE69615538 T2 DE 69615538T2
Authority
DE
Germany
Prior art keywords
memory cells
memory
programming
defective
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69615538T
Other languages
English (en)
Other versions
DE69615538D1 (de
Inventor
E O'toole
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE69615538D1 publication Critical patent/DE69615538D1/de
Application granted granted Critical
Publication of DE69615538T2 publication Critical patent/DE69615538T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/76Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G11C29/765Masking faults in memories by using spares or by reconfiguring using address translation or modifications in solid state disks
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44Indication or identification of errors, e.g. for repair
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52Protection of memory contents; Detection of errors in memory contents
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/78Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
    • G11C29/82Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for EEPROMs
DE69615538T 1995-02-13 1996-02-07 Integrierte speicherredundanzschaltung für programmierbare festwertspeicher und progammierungsverfahren Expired - Lifetime DE69615538T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/387,244 US5513144A (en) 1995-02-13 1995-02-13 On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same
PCT/US1996/001756 WO1996025744A1 (en) 1995-02-13 1996-02-07 On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same

Publications (2)

Publication Number Publication Date
DE69615538D1 DE69615538D1 (de) 2001-10-31
DE69615538T2 true DE69615538T2 (de) 2002-05-08

Family

ID=23529081

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69615538T Expired - Lifetime DE69615538T2 (de) 1995-02-13 1996-02-07 Integrierte speicherredundanzschaltung für programmierbare festwertspeicher und progammierungsverfahren

Country Status (8)

Country Link
US (3) US5513144A (de)
EP (1) EP0809849B1 (de)
JP (1) JP3764167B2 (de)
KR (1) KR100386132B1 (de)
AT (1) ATE206241T1 (de)
DE (1) DE69615538T2 (de)
TW (1) TW290690B (de)
WO (1) WO1996025744A1 (de)

Families Citing this family (148)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5657332A (en) * 1992-05-20 1997-08-12 Sandisk Corporation Soft errors handling in EEPROM devices
US5513144A (en) * 1995-02-13 1996-04-30 Micron Technology, Inc. On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same
US5838620A (en) * 1995-04-05 1998-11-17 Micron Technology, Inc. Circuit for cancelling and replacing redundant elements
EP0798642B1 (de) * 1996-03-29 2001-11-07 STMicroelectronics S.r.l. Redundanzverwaltungsverfahren und -architektur, insbesondere für nicht-flüchtige Speicher
US5724282A (en) * 1996-09-06 1998-03-03 Micron Technology, Inc. System and method for an antifuse bank
US5771346A (en) * 1996-10-24 1998-06-23 Micron Quantum Devices, Inc. Apparatus and method for detecting over-programming condition in multistate memory device
US5764568A (en) * 1996-10-24 1998-06-09 Micron Quantum Devices, Inc. Method for performing analog over-program and under-program detection for a multistate memory cell
US5768287A (en) 1996-10-24 1998-06-16 Micron Quantum Devices, Inc. Apparatus and method for programming multistate memory device
US5732033A (en) * 1996-11-14 1998-03-24 Micron Technology, Inc. Method and circuit for rapidly equilibrating paired digit lines of a memory device during testing
US10839321B2 (en) * 1997-01-06 2020-11-17 Jeffrey Eder Automated data storage system
US5912579A (en) * 1997-02-06 1999-06-15 Zagar; Paul S. Circuit for cancelling and replacing redundant elements
US5909049A (en) 1997-02-11 1999-06-01 Actel Corporation Antifuse programmed PROM cell
US5935258A (en) * 1997-03-04 1999-08-10 Micron Electronics, Inc. Apparatus for allowing data transfers with a memory having defective storage locations
US5970022A (en) * 1997-03-21 1999-10-19 Winbond Electronics Corporation Semiconductor memory device with reduced read disturbance
US5910921A (en) * 1997-04-22 1999-06-08 Micron Technology, Inc. Self-test of a memory device
US6172935B1 (en) 1997-04-25 2001-01-09 Micron Technology, Inc. Synchronous dynamic random access memory device
US5881003A (en) * 1997-07-16 1999-03-09 International Business Machines Corporation Method of making a memory device fault tolerant using a variable domain redundancy replacement configuration
US5909449A (en) * 1997-09-08 1999-06-01 Invox Technology Multibit-per-cell non-volatile memory with error detection and correction
US6011733A (en) * 1998-02-26 2000-01-04 Lucent Technologies Inc. Adaptive addressable circuit redundancy method and apparatus
US5970013A (en) * 1998-02-26 1999-10-19 Lucent Technologies Inc. Adaptive addressable circuit redundancy method and apparatus with broadcast write
JP2000048567A (ja) * 1998-05-22 2000-02-18 Mitsubishi Electric Corp 同期型半導体記憶装置
US6122203A (en) * 1998-06-29 2000-09-19 Cypress Semiconductor Corp. Method, architecture and circuit for writing to and reading from a memory during a single cycle
US5986970A (en) * 1998-06-29 1999-11-16 Cypress Semiconductor Corp. Method, architecture and circuit for writing to a memory
KR100333720B1 (ko) * 1998-06-30 2002-06-20 박종섭 강유전체메모리소자의리던던시회로
US6289438B1 (en) * 1998-07-29 2001-09-11 Kabushiki Kaisha Toshiba Microprocessor cache redundancy scheme using store buffer
US6910152B2 (en) * 1998-08-28 2005-06-21 Micron Technology, Inc. Device and method for repairing a semiconductor memory
US6199177B1 (en) 1998-08-28 2001-03-06 Micron Technology, Inc. Device and method for repairing a semiconductor memory
JP2000076898A (ja) * 1998-08-31 2000-03-14 Mitsubishi Electric Corp 半導体メモリ装置、その検査方法、および、その製造方法
US6567302B2 (en) 1998-12-29 2003-05-20 Micron Technology, Inc. Method and apparatus for programming multi-state cells in a memory device
US6438672B1 (en) 1999-06-03 2002-08-20 Agere Systems Guardian Corp. Memory aliasing method and apparatus
JP4251717B2 (ja) * 1999-06-03 2009-04-08 富士通マイクロエレクトロニクス株式会社 不揮発性半導体記憶装置
US6687814B1 (en) * 1999-07-12 2004-02-03 Micron Technology, Inc. Controller with interface attachment
US6484271B1 (en) 1999-09-16 2002-11-19 Koninklijke Philips Electronics N.V. Memory redundancy techniques
US6574763B1 (en) 1999-12-28 2003-06-03 International Business Machines Corporation Method and apparatus for semiconductor integrated circuit testing and burn-in
JP3893005B2 (ja) * 2000-01-06 2007-03-14 富士通株式会社 不揮発性半導体記憶装置
US20020196687A1 (en) * 2001-06-08 2002-12-26 Sauvageau Anthony J. Methods and apparatus for analyzing and repairing memory
JP2003022693A (ja) * 2001-07-09 2003-01-24 Mitsubishi Electric Corp 半導体メモリ
US7219271B2 (en) * 2001-12-14 2007-05-15 Sandisk 3D Llc Memory device and method for redundancy/self-repair
US7047465B1 (en) 2002-02-28 2006-05-16 Xilinx, Inc. Methods for using defective programmable logic devices by customizing designs based on recorded defects
DE60212332T2 (de) * 2002-04-26 2007-06-06 Stmicroelectronics S.R.L., Agrate Brianza Selbstreparatur-Methode für nicht flüchtige Speicher mit einer Architektur zur Fehlervermeidung sowie nicht flüchtiger Speicher
EP1365419B1 (de) 2002-05-21 2008-12-31 STMicroelectronics S.r.l. Selbstreparaturverfahren für nichtflüchtige Speicheranordnung mit Lösch-/Programmierfehlerdetektion, und nichtflüchtige Speicheranordnung dafür
EP1403879B1 (de) * 2002-09-30 2010-11-03 STMicroelectronics Srl Verfahren zur Ersetzung von ausgefallenen nichtflüchtigen Speicherzellen und dementsprechende Speicheranordnung
US6868022B2 (en) * 2003-03-28 2005-03-15 Matrix Semiconductor, Inc. Redundant memory structure using bad bit pointers
US7000155B2 (en) * 2003-04-21 2006-02-14 International Business Machines Corporation Redundancy register architecture for soft-error tolerance and methods of making the same
US8788996B2 (en) * 2003-09-15 2014-07-22 Nvidia Corporation System and method for configuring semiconductor functional circuits
US8732644B1 (en) 2003-09-15 2014-05-20 Nvidia Corporation Micro electro mechanical switch system and method for testing and configuring semiconductor functional circuits
US8775997B2 (en) 2003-09-15 2014-07-08 Nvidia Corporation System and method for testing and configuring semiconductor functional circuits
US7012835B2 (en) * 2003-10-03 2006-03-14 Sandisk Corporation Flash memory data correction and scrub techniques
US7173852B2 (en) * 2003-10-03 2007-02-06 Sandisk Corporation Corrected data storage and handling methods
US7216277B1 (en) 2003-11-18 2007-05-08 Xilinx, Inc. Self-repairing redundancy for memory blocks in programmable logic devices
US8711161B1 (en) * 2003-12-18 2014-04-29 Nvidia Corporation Functional component compensation reconfiguration system and method
US8723231B1 (en) * 2004-09-15 2014-05-13 Nvidia Corporation Semiconductor die micro electro-mechanical switch management system and method
US8711156B1 (en) 2004-09-30 2014-04-29 Nvidia Corporation Method and system for remapping processing elements in a pipeline of a graphics processing unit
US7424655B1 (en) 2004-10-01 2008-09-09 Xilinx, Inc. Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits
US7284229B1 (en) 2004-10-01 2007-10-16 Xilinx, Inc. Multiple bitstreams enabling the use of partially defective programmable integrated circuits while avoiding localized defects therein
US7412635B1 (en) 2004-10-01 2008-08-12 Xilinx, Inc. Utilizing multiple bitstreams to avoid localized defects in partially defective programmable integrated circuits
US7251804B1 (en) 2004-10-01 2007-07-31 Xilinx, Inc. Structures and methods of overcoming localized defects in programmable integrated circuits by routing during the programming thereof
US7395404B2 (en) * 2004-12-16 2008-07-01 Sandisk Corporation Cluster auto-alignment for storing addressable data packets in a non-volatile memory array
US7315916B2 (en) * 2004-12-16 2008-01-01 Sandisk Corporation Scratch pad block
US7277336B2 (en) * 2004-12-28 2007-10-02 Sandisk 3D Llc Method and apparatus for improving yield in semiconductor devices by guaranteeing health of redundancy information
ITMI20042538A1 (it) * 2004-12-29 2005-03-29 Atmel Corp Metodo e sistema per la riduzione del soft-writing in una memoria flash a livelli multipli
WO2006085633A1 (en) * 2005-02-10 2006-08-17 Semiconductor Energy Laboratory Co., Ltd. Memory element and semiconductor device
US8021193B1 (en) 2005-04-25 2011-09-20 Nvidia Corporation Controlled impedance display adapter
US7793029B1 (en) 2005-05-17 2010-09-07 Nvidia Corporation Translation device apparatus for configuring printed circuit board connectors
US7212454B2 (en) * 2005-06-22 2007-05-01 Sandisk 3D Llc Method and apparatus for programming a memory array
US9092170B1 (en) 2005-10-18 2015-07-28 Nvidia Corporation Method and system for implementing fragment operation processing across a graphics bus interconnect
US8412872B1 (en) 2005-12-12 2013-04-02 Nvidia Corporation Configurable GPU and method for graphics processing using a configurable GPU
US8417838B2 (en) * 2005-12-12 2013-04-09 Nvidia Corporation System and method for configurable digital communication
US20070136640A1 (en) * 2005-12-14 2007-06-14 Jarrar Anis M Defect detection and repair in an embedded random access memory
US7324389B2 (en) * 2006-03-24 2008-01-29 Sandisk Corporation Non-volatile memory with redundancy data buffered in remote buffer circuits
US7567461B2 (en) * 2006-08-18 2009-07-28 Micron Technology, Inc. Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells
US7716538B2 (en) * 2006-09-27 2010-05-11 Sandisk Corporation Memory with cell population distribution assisted read margining
US7886204B2 (en) * 2006-09-27 2011-02-08 Sandisk Corporation Methods of cell population distribution assisted read margining
US7477547B2 (en) * 2007-03-28 2009-01-13 Sandisk Corporation Flash memory refresh techniques triggered by controlled scrub data reads
US7573773B2 (en) * 2007-03-28 2009-08-11 Sandisk Corporation Flash memory with data refresh triggered by controlled scrub data reads
US7958390B2 (en) * 2007-05-15 2011-06-07 Sandisk Corporation Memory device for repairing a neighborhood of rows in a memory array using a patch table
US7966518B2 (en) * 2007-05-15 2011-06-21 Sandisk Corporation Method for repairing a neighborhood of rows in a memory array using a patch table
US7853916B1 (en) 2007-10-11 2010-12-14 Xilinx, Inc. Methods of using one of a plurality of configuration bitstreams for an integrated circuit
US7619438B1 (en) 2007-10-11 2009-11-17 Xilinx, Inc. Methods of enabling the use of a defective programmable device
US7810059B1 (en) 2007-10-11 2010-10-05 Xilinx, Inc. Methods of enabling the validation of an integrated circuit adapted to receive one of a plurality of configuration bitstreams
US8724483B2 (en) * 2007-10-22 2014-05-13 Nvidia Corporation Loopback configuration for bi-directional interfaces
US20090119444A1 (en) * 2007-11-01 2009-05-07 Zerog Wireless, Inc., Delaware Corporation Multiple write cycle memory using redundant addressing
TWI360061B (en) 2007-12-31 2012-03-11 Htc Corp Electronic device and method for operating applica
TWI381390B (zh) * 2008-04-10 2013-01-01 Phison Electronics Corp 快閃記憶體的損壞區塊辨識方法、儲存系統及其控制器
US8687639B2 (en) * 2009-06-04 2014-04-01 Nvidia Corporation Method and system for ordering posted packets and non-posted packets transfer
US8371094B2 (en) * 2009-10-23 2013-02-12 Frito-Lay North America, Inc. Method and apparatus for compacting product
US9284075B2 (en) 2009-10-23 2016-03-15 Frito-Lay North America, Inc. Apparatus for compacting product and high speed bagmaking
US9176909B2 (en) 2009-12-11 2015-11-03 Nvidia Corporation Aggregating unoccupied PCI-e links to provide greater bandwidth
US9331869B2 (en) * 2010-03-04 2016-05-03 Nvidia Corporation Input/output request packet handling techniques by a device specific kernel mode driver
US9202569B2 (en) 2011-08-12 2015-12-01 Micron Technology, Inc. Methods for providing redundancy and apparatuses
US8687421B2 (en) 2011-11-21 2014-04-01 Sandisk Technologies Inc. Scrub techniques for use with dynamic read
US9330031B2 (en) 2011-12-09 2016-05-03 Nvidia Corporation System and method for calibration of serial links using a serial-to-parallel loopback
US9230689B2 (en) 2014-03-17 2016-01-05 Sandisk Technologies Inc. Finding read disturbs on non-volatile memories
US9552171B2 (en) 2014-10-29 2017-01-24 Sandisk Technologies Llc Read scrub with adaptive counter management
US9978456B2 (en) 2014-11-17 2018-05-22 Sandisk Technologies Llc Techniques for reducing read disturb in partially written blocks of non-volatile memory
US9349479B1 (en) 2014-11-18 2016-05-24 Sandisk Technologies Inc. Boundary word line operation in nonvolatile memory
US9449700B2 (en) 2015-02-13 2016-09-20 Sandisk Technologies Llc Boundary word line search and open block read methods with reduced read disturb
US10163479B2 (en) 2015-08-14 2018-12-25 Spin Transfer Technologies, Inc. Method and apparatus for bipolar memory write-verify
US9653154B2 (en) 2015-09-21 2017-05-16 Sandisk Technologies Llc Write abort detection for multi-state memories
US10192601B2 (en) 2016-09-27 2019-01-29 Spin Transfer Technologies, Inc. Memory instruction pipeline with an additional write stage in a memory device that uses dynamic redundancy registers
US10818331B2 (en) 2016-09-27 2020-10-27 Spin Memory, Inc. Multi-chip module for MRAM devices with levels of dynamic redundancy registers
US10546625B2 (en) 2016-09-27 2020-01-28 Spin Memory, Inc. Method of optimizing write voltage based on error buffer occupancy
US10628316B2 (en) 2016-09-27 2020-04-21 Spin Memory, Inc. Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register
US10360964B2 (en) 2016-09-27 2019-07-23 Spin Memory, Inc. Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device
US10460781B2 (en) 2016-09-27 2019-10-29 Spin Memory, Inc. Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank
US10366774B2 (en) * 2016-09-27 2019-07-30 Spin Memory, Inc. Device with dynamic redundancy registers
US10437723B2 (en) 2016-09-27 2019-10-08 Spin Memory, Inc. Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device
US10446210B2 (en) 2016-09-27 2019-10-15 Spin Memory, Inc. Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers
US10192602B2 (en) 2016-09-27 2019-01-29 Spin Transfer Technologies, Inc. Smart cache design to prevent overflow for a memory device with a dynamic redundancy register
US10437491B2 (en) 2016-09-27 2019-10-08 Spin Memory, Inc. Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register
EP3367385B1 (de) * 2017-02-28 2020-07-08 ams AG Speicheranordnung und verfahren zum betrieb einer speicheranordnung
US10489245B2 (en) 2017-10-24 2019-11-26 Spin Memory, Inc. Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct them
US10481976B2 (en) 2017-10-24 2019-11-19 Spin Memory, Inc. Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers
US10529439B2 (en) 2017-10-24 2020-01-07 Spin Memory, Inc. On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects
US10656994B2 (en) 2017-10-24 2020-05-19 Spin Memory, Inc. Over-voltage write operation of tunnel magnet-resistance (“TMR”) memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniques
US10811594B2 (en) 2017-12-28 2020-10-20 Spin Memory, Inc. Process for hard mask development for MRAM pillar formation using photolithography
US10424726B2 (en) 2017-12-28 2019-09-24 Spin Memory, Inc. Process for improving photoresist pillar adhesion during MRAM fabrication
US10360962B1 (en) 2017-12-28 2019-07-23 Spin Memory, Inc. Memory array with individually trimmable sense amplifiers
US10395712B2 (en) 2017-12-28 2019-08-27 Spin Memory, Inc. Memory array with horizontal source line and sacrificial bitline per virtual source
US10516094B2 (en) 2017-12-28 2019-12-24 Spin Memory, Inc. Process for creating dense pillars using multiple exposures for MRAM fabrication
US10395711B2 (en) 2017-12-28 2019-08-27 Spin Memory, Inc. Perpendicular source and bit lines for an MRAM array
US10891997B2 (en) 2017-12-28 2021-01-12 Spin Memory, Inc. Memory array with horizontal source line and a virtual source line
US10784439B2 (en) 2017-12-29 2020-09-22 Spin Memory, Inc. Precessional spin current magnetic tunnel junction devices and methods of manufacture
US10840436B2 (en) 2017-12-29 2020-11-17 Spin Memory, Inc. Perpendicular magnetic anisotropy interface tunnel junction devices and methods of manufacture
US10546624B2 (en) 2017-12-29 2020-01-28 Spin Memory, Inc. Multi-port random access memory
US10840439B2 (en) 2017-12-29 2020-11-17 Spin Memory, Inc. Magnetic tunnel junction (MTJ) fabrication methods and systems
US10886330B2 (en) 2017-12-29 2021-01-05 Spin Memory, Inc. Memory device having overlapping magnetic tunnel junctions in compliance with a reference pitch
US10367139B2 (en) 2017-12-29 2019-07-30 Spin Memory, Inc. Methods of manufacturing magnetic tunnel junction devices
US10424723B2 (en) 2017-12-29 2019-09-24 Spin Memory, Inc. Magnetic tunnel junction devices including an optimization layer
US10438995B2 (en) 2018-01-08 2019-10-08 Spin Memory, Inc. Devices including magnetic tunnel junctions integrated with selectors
US10438996B2 (en) 2018-01-08 2019-10-08 Spin Memory, Inc. Methods of fabricating magnetic tunnel junctions integrated with selectors
US10446744B2 (en) 2018-03-08 2019-10-15 Spin Memory, Inc. Magnetic tunnel junction wafer adaptor used in magnetic annealing furnace and method of using the same
US10784437B2 (en) 2018-03-23 2020-09-22 Spin Memory, Inc. Three-dimensional arrays with MTJ devices including a free magnetic trench layer and a planar reference magnetic layer
US11107978B2 (en) 2018-03-23 2021-08-31 Spin Memory, Inc. Methods of manufacturing three-dimensional arrays with MTJ devices including a free magnetic trench layer and a planar reference magnetic layer
US11107974B2 (en) 2018-03-23 2021-08-31 Spin Memory, Inc. Magnetic tunnel junction devices including a free magnetic trench layer and a planar reference magnetic layer
US20190296220A1 (en) 2018-03-23 2019-09-26 Spin Transfer Technologies, Inc. Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer
US10411185B1 (en) 2018-05-30 2019-09-10 Spin Memory, Inc. Process for creating a high density magnetic tunnel junction array test platform
US10559338B2 (en) 2018-07-06 2020-02-11 Spin Memory, Inc. Multi-bit cell read-out techniques
US10600478B2 (en) 2018-07-06 2020-03-24 Spin Memory, Inc. Multi-bit cell read-out techniques for MRAM cells with mixed pinned magnetization orientations
US10593396B2 (en) 2018-07-06 2020-03-17 Spin Memory, Inc. Multi-bit cell read-out techniques for MRAM cells with mixed pinned magnetization orientations
US10692569B2 (en) 2018-07-06 2020-06-23 Spin Memory, Inc. Read-out techniques for multi-bit cells
US10990472B2 (en) 2018-07-24 2021-04-27 Micron Technology, Inc. Spare substitution in memory system
US10650875B2 (en) 2018-08-21 2020-05-12 Spin Memory, Inc. System for a wide temperature range nonvolatile memory
US10699761B2 (en) 2018-09-18 2020-06-30 Spin Memory, Inc. Word line decoder memory architecture
US11621293B2 (en) 2018-10-01 2023-04-04 Integrated Silicon Solution, (Cayman) Inc. Multi terminal device stack systems and methods
US10971680B2 (en) 2018-10-01 2021-04-06 Spin Memory, Inc. Multi terminal device stack formation methods
US11107979B2 (en) 2018-12-28 2021-08-31 Spin Memory, Inc. Patterned silicide structures and methods of manufacture
KR20210157862A (ko) * 2020-06-22 2021-12-29 에스케이하이닉스 주식회사 메모리, 메모리 시스템 및 메모리 시스템의 동작 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0283899A (ja) * 1988-09-20 1990-03-23 Fujitsu Ltd 半導体記憶装置
GB8901093D0 (en) * 1989-01-18 1989-03-15 Almond Jeffrey W Attenuated viruses
US5289413A (en) * 1990-06-08 1994-02-22 Kabushiki Kaisha Toshiba Dynamic semiconductor memory device with high-speed serial-accessing column decoder
US5237535A (en) * 1991-10-09 1993-08-17 Intel Corporation Method of repairing overerased cells in a flash memory
JP2716906B2 (ja) * 1992-03-27 1998-02-18 株式会社東芝 不揮発性半導体記憶装置
US5347489A (en) * 1992-04-21 1994-09-13 Intel Corporation Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy
EP0596198B1 (de) * 1992-07-10 2000-03-29 Sony Corporation Flash-EPROM mit Löschprüfung und Architektur zum Adresszerhacken
JP3001342B2 (ja) * 1993-02-10 2000-01-24 日本電気株式会社 記憶装置
JPH06259987A (ja) * 1993-03-10 1994-09-16 Mitsubishi Electric Corp 半導体記憶装置
US5513144A (en) * 1995-02-13 1996-04-30 Micron Technology, Inc. On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same

Also Published As

Publication number Publication date
US5513144A (en) 1996-04-30
US5751647A (en) 1998-05-12
DE69615538D1 (de) 2001-10-31
JPH11500561A (ja) 1999-01-12
WO1996025744A1 (en) 1996-08-22
US5648934A (en) 1997-07-15
EP0809849A1 (de) 1997-12-03
KR19980702143A (ko) 1998-07-15
JP3764167B2 (ja) 2006-04-05
KR100386132B1 (ko) 2003-08-19
TW290690B (de) 1996-11-11
EP0809849B1 (de) 2001-09-26
ATE206241T1 (de) 2001-10-15

Similar Documents

Publication Publication Date Title
DE69615538T2 (de) Integrierte speicherredundanzschaltung für programmierbare festwertspeicher und progammierungsverfahren
US7301832B2 (en) Compact column redundancy CAM architecture for concurrent read and write operations in multi-segment memory arrays
US4517663A (en) Method of rewriting data in non-volatile memory, and system therefor
US6614689B2 (en) Non-volatile memory having a control mini-array
US6108236A (en) Smart card comprising integrated circuitry including EPROM and error check and correction system
WO1994007211A3 (en) Latent defect handling in eeprom devices
TW358208B (en) Non-volatile semiconductor memory for unit and multi-unit operations
DE102007058418A1 (de) Fehlerkorrektur in Speicherbauteilen
JPS61267846A (ja) メモリを有する集積回路装置
DE69426817D1 (de) Fertigungprüfungsverfahren von Flash-EEPROM-Vorrichtungen
DE69412230T2 (de) Verfahren zur Programmierung von Redundanzregistern in einer Spaltenredundanzschaltung für einen Halbleiterspeicherbaustein
JP2540028B2 (ja) 集積プログラミング回路
US5986965A (en) Method and device for writing data in non-volatile memory circuit
JP3542637B2 (ja) 電流測定方法及びマイクロコントローラシステム
US6549468B2 (en) Non-volatile memory with address descrambling
JP2003122638A (ja) 半導体集積回路装置
JP2003187591A5 (de)
US4032765A (en) Memory modification system
KR20010051873A (ko) 메모리 셀 및 기준 셀을 포함하는 집적 메모리
JPH0799636B2 (ja) 半導体記憶装置
KR960000771Y1 (ko) 뱅크절환기능을 갖춘 불휘발성 반도체 기억장치
JPS62107520A (ja) プログラマブル・ロジツク・アレイ
JPH0528798A (ja) 半導体メモリの検定装置
ES2078916T3 (es) Dispositivo para comprobar la capacidad de funcion de ubicaciones de almacenamiento de una memoria escritura-lectura.
EP0029304A3 (de) Blasenspeichervorrichtung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition