DE69618319D1 - Mehrbankenspeicherarchitektur und Systeme und Verfahren unter Verwendung derselben - Google Patents

Mehrbankenspeicherarchitektur und Systeme und Verfahren unter Verwendung derselben

Info

Publication number
DE69618319D1
DE69618319D1 DE69618319T DE69618319T DE69618319D1 DE 69618319 D1 DE69618319 D1 DE 69618319D1 DE 69618319 T DE69618319 T DE 69618319T DE 69618319 T DE69618319 T DE 69618319T DE 69618319 D1 DE69618319 D1 DE 69618319D1
Authority
DE
Germany
Prior art keywords
systems
methods
same
memory architecture
bank memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69618319T
Other languages
English (en)
Other versions
DE69618319T2 (de
Inventor
G R Mohan Rao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cirrus Logic Inc
Original Assignee
Cirrus Logic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24190263&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69618319(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Cirrus Logic Inc filed Critical Cirrus Logic Inc
Publication of DE69618319D1 publication Critical patent/DE69618319D1/de
Application granted granted Critical
Publication of DE69618319T2 publication Critical patent/DE69618319T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
DE69618319T 1995-10-26 1996-10-25 Mehrbankenspeicherarchitektur und Systeme und Verfahren unter Verwendung derselben Expired - Fee Related DE69618319T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/548,752 US5687132A (en) 1995-10-26 1995-10-26 Multiple-bank memory architecture and systems and methods using the same

Publications (2)

Publication Number Publication Date
DE69618319D1 true DE69618319D1 (de) 2002-02-07
DE69618319T2 DE69618319T2 (de) 2002-08-14

Family

ID=24190263

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69618319T Expired - Fee Related DE69618319T2 (de) 1995-10-26 1996-10-25 Mehrbankenspeicherarchitektur und Systeme und Verfahren unter Verwendung derselben

Country Status (6)

Country Link
US (1) US5687132A (de)
EP (1) EP0771008B1 (de)
JP (1) JP2828626B2 (de)
KR (1) KR100258672B1 (de)
DE (1) DE69618319T2 (de)
HK (1) HK1010017A1 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08123953A (ja) * 1994-10-21 1996-05-17 Mitsubishi Electric Corp 画像処理装置
US5844856A (en) * 1996-06-19 1998-12-01 Cirrus Logic, Inc. Dual port memories and systems and methods using the same
US6510098B1 (en) * 1997-05-28 2003-01-21 Cirrus Logic, Inc. Method and apparatus for transferring data in a dual port memory
JP2000195264A (ja) * 1998-12-25 2000-07-14 Oki Micro Design Co Ltd 半導体記憶装置
US6046958A (en) * 1999-01-11 2000-04-04 Micron Technology, Inc. Latching wordline driver for multi-bank memory
US6445636B1 (en) * 2000-08-17 2002-09-03 Micron Technology, Inc. Method and system for hiding refreshes in a dynamic random access memory
US6545935B1 (en) * 2000-08-29 2003-04-08 Ibm Corporation Dual-port DRAM architecture system
US20050280623A1 (en) * 2000-12-18 2005-12-22 Renesas Technology Corp. Display control device and mobile electronic apparatus
JP4132654B2 (ja) * 2000-12-18 2008-08-13 株式会社ルネサステクノロジ 表示制御装置および携帯用電子機器
CA2340985A1 (en) * 2001-03-14 2002-09-14 Atmos Corporation Interleaved wordline architecture
US6519174B2 (en) 2001-05-16 2003-02-11 International Business Machines Corporation Early write DRAM architecture with vertically folded bitlines
US20050185465A1 (en) * 2003-03-11 2005-08-25 Fujitsu Limited Memory device
JP4523348B2 (ja) * 2004-07-06 2010-08-11 株式会社 日立ディスプレイズ 表示装置及びその駆動方法
US7295485B2 (en) * 2005-07-12 2007-11-13 Atmel Corporation Memory architecture with advanced main-bitline partitioning circuitry for enhanced erase/program/verify operations
US8120613B2 (en) * 2006-11-29 2012-02-21 Siemens Medical Solutions Usa, Inc. Method and apparatus for real-time digital image acquisition, storage, and retrieval
JP5018074B2 (ja) * 2006-12-22 2012-09-05 富士通セミコンダクター株式会社 メモリ装置，メモリコントローラ及びメモリシステム
US20090257263A1 (en) * 2008-04-15 2009-10-15 Vns Portfolio Llc Method and Apparatus for Computer Memory
WO2011094437A2 (en) 2010-01-28 2011-08-04 Hewlett-Packard Development Company, L.P. Memory access methods and apparatus
US9146867B2 (en) 2011-10-31 2015-09-29 Hewlett-Packard Development Company, L.P. Methods and apparatus to access memory using runtime characteristics
US20140173170A1 (en) * 2012-12-14 2014-06-19 Hewlett-Packard Development Company, L.P. Multiple subarray memory access
KR102193444B1 (ko) * 2014-04-28 2020-12-21 삼성전자주식회사 반도체 메모리 장치 및 이를 포함하는 메모리 시스템

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE66314T1 (de) * 1985-08-30 1991-08-15 Sgs Thomson Microelectronics Parallele zeile pro zeile datenuebertragung in ram-speichern.
JPS6284495A (ja) * 1985-10-08 1987-04-17 Nippon Texas Instr Kk 半導体記憶装置
JPS63898A (ja) * 1986-06-19 1988-01-05 Fujitsu Ltd 半導体記憶装置
JPS63183694A (ja) * 1987-01-23 1988-07-29 Mitsubishi Electric Corp 半導体記憶装置
JPS63255747A (ja) * 1987-04-13 1988-10-24 Mitsubishi Electric Corp 画像メモリ装置
JPH01224993A (ja) * 1988-03-04 1989-09-07 Nec Corp マルチポートメモリ
JP2993671B2 (ja) * 1989-01-07 1999-12-20 三菱電機株式会社 半導体記憶装置
KR950003605B1 (ko) * 1990-04-27 1995-04-14 가부시키가이샤 도시바 반도체 기억장치
US5121360A (en) * 1990-06-19 1992-06-09 International Business Machines Corporation Video random access memory serial port access
JPH04307495A (ja) * 1991-04-04 1992-10-29 Mitsubishi Electric Corp 半導体記憶装置
JP2696026B2 (ja) * 1991-11-21 1998-01-14 株式会社東芝 半導体記憶装置
US5377154A (en) * 1992-01-31 1994-12-27 Oki Electric Industry Co., Ltd. Multiple serial-access memory
US5390139A (en) * 1993-05-28 1995-02-14 Texas Instruments Incorporated Devices, systems and methods for implementing a Kanerva memory
JPH07192454A (ja) * 1993-12-27 1995-07-28 Matsushita Electric Ind Co Ltd 半導体メモリおよび画像処理装置

Also Published As

Publication number Publication date
JP2828626B2 (ja) 1998-11-25
EP0771008A3 (de) 1998-04-01
EP0771008B1 (de) 2002-01-02
US5687132A (en) 1997-11-11
EP0771008A2 (de) 1997-05-02
DE69618319T2 (de) 2002-08-14
KR100258672B1 (ko) 2000-06-15
JPH09231746A (ja) 1997-09-05
HK1010017A1 (en) 1999-06-11
KR970022773A (ko) 1997-05-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee