DE69626070T2 - Verfahren und Vorrichtung zum Etikettieren eines Mehrweg-assoziativen Cache-Speichers - Google Patents

Verfahren und Vorrichtung zum Etikettieren eines Mehrweg-assoziativen Cache-Speichers

Info

Publication number
DE69626070T2
DE69626070T2 DE69626070T DE69626070T DE69626070T2 DE 69626070 T2 DE69626070 T2 DE 69626070T2 DE 69626070 T DE69626070 T DE 69626070T DE 69626070 T DE69626070 T DE 69626070T DE 69626070 T2 DE69626070 T2 DE 69626070T2
Authority
DE
Germany
Prior art keywords
labeling
associative cache
way associative
way
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69626070T
Other languages
English (en)
Other versions
DE69626070D1 (de
Inventor
Erik Hagersten
Ashok Singhal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of DE69626070D1 publication Critical patent/DE69626070D1/de
Publication of DE69626070T2 publication Critical patent/DE69626070T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/608—Details relating to cache mapping
    • G06F2212/6082—Way prediction in set-associative cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69626070T 1995-07-07 1996-07-05 Verfahren und Vorrichtung zum Etikettieren eines Mehrweg-assoziativen Cache-Speichers Expired - Fee Related DE69626070T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/499,590 US5778427A (en) 1995-07-07 1995-07-07 Method and apparatus for selecting a way of a multi-way associative cache by storing waylets in a translation structure

Publications (2)

Publication Number Publication Date
DE69626070D1 DE69626070D1 (de) 2003-03-13
DE69626070T2 true DE69626070T2 (de) 2003-09-25

Family

ID=23985861

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69626070T Expired - Fee Related DE69626070T2 (de) 1995-07-07 1996-07-05 Verfahren und Vorrichtung zum Etikettieren eines Mehrweg-assoziativen Cache-Speichers

Country Status (4)

Country Link
US (1) US5778427A (de)
EP (1) EP0752662B1 (de)
JP (1) JPH09223067A (de)
DE (1) DE69626070T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6026413A (en) * 1997-08-01 2000-02-15 International Business Machines Corporation Determining how changes to underlying data affect cached objects
US6256712B1 (en) 1997-08-01 2001-07-03 International Business Machines Corporation Scaleable method for maintaining and making consistent updates to caches
US6212602B1 (en) * 1997-12-17 2001-04-03 Sun Microsystems, Inc. Cache tag caching
US6622208B2 (en) * 2001-03-30 2003-09-16 Cirrus Logic, Inc. System and methods using a system-on-a-chip with soft cache
KR100389867B1 (ko) * 2001-06-04 2003-07-04 삼성전자주식회사 플래시 메모리 관리방법
US6678792B2 (en) * 2001-06-22 2004-01-13 Koninklijke Philips Electronics N.V. Fast and accurate cache way selection
DE10158393A1 (de) 2001-11-28 2003-06-12 Infineon Technologies Ag Speicher für die Zentraleinheit einer Rechenanlage, Rechenanlage und Verfahren zum Synchronisieren eines Speichers mit dem Hauptspeicher einer Rechenanlage
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
JP2005215911A (ja) * 2004-01-29 2005-08-11 Hitachi Ltd 情報処理装置
US7237067B2 (en) * 2004-04-22 2007-06-26 Hewlett-Packard Development Company, L.P. Managing a multi-way associative cache
US7533198B2 (en) * 2005-10-07 2009-05-12 International Business Machines Corporation Memory controller and method for handling DMA operations during a page copy
US7725620B2 (en) * 2005-10-07 2010-05-25 International Business Machines Corporation Handling DMA requests in a virtual memory environment
TWI377473B (en) * 2008-11-21 2012-11-21 Sunplus Innovation Technology Inc Serial interface cache controller, control method and micro-controller system using the same
US8806137B2 (en) * 2011-06-17 2014-08-12 Lsi Corporation Cache replacement using active cache line counters
US9684601B2 (en) * 2012-05-10 2017-06-20 Arm Limited Data processing apparatus having cache and translation lookaside buffer
US10671543B2 (en) * 2013-11-21 2020-06-02 Samsung Electronics Co., Ltd. Systems and methods for reducing first level cache energy by eliminating cache address tags
US10402331B2 (en) 2014-05-29 2019-09-03 Samsung Electronics Co., Ltd. Systems and methods for implementing a tag-less shared cache and a larger backing cache
CN105208596A (zh) * 2014-06-17 2015-12-30 中兴通讯股份有限公司 一种表头压缩方法、解压方法及装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3699533A (en) * 1970-10-29 1972-10-17 Rca Corp Memory system including buffer memories
US5341483A (en) * 1987-12-22 1994-08-23 Kendall Square Research Corporation Dynamic hierarchial associative memory
US5055999A (en) * 1987-12-22 1991-10-08 Kendall Square Research Corporation Multiprocessor digital data processing system
ATE170642T1 (de) * 1990-06-15 1998-09-15 Compaq Computer Corp Mehrstufeneinschluss in mehrstufigen cache- speicherhierarchien
US5235697A (en) * 1990-06-29 1993-08-10 Digital Equipment Set prediction cache memory system using bits of the main memory address
US5418922A (en) * 1992-04-30 1995-05-23 International Business Machines Corporation History table for set prediction for accessing a set associative cache
US5640532A (en) * 1994-10-14 1997-06-17 Compaq Computer Corporation Microprocessor cache memory way prediction based on the way of previous memory read

Also Published As

Publication number Publication date
EP0752662A1 (de) 1997-01-08
DE69626070D1 (de) 2003-03-13
US5778427A (en) 1998-07-07
EP0752662B1 (de) 2003-02-05
JPH09223067A (ja) 1997-08-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee