DE69627240D1 - Synchronisierte Datenübermittlung zwischen Einheiten eines Verarbeitungssystems - Google Patents

Synchronisierte Datenübermittlung zwischen Einheiten eines Verarbeitungssystems

Info

Publication number
DE69627240D1
DE69627240D1 DE69627240T DE69627240T DE69627240D1 DE 69627240 D1 DE69627240 D1 DE 69627240D1 DE 69627240 T DE69627240 T DE 69627240T DE 69627240 T DE69627240 T DE 69627240T DE 69627240 D1 DE69627240 D1 DE 69627240D1
Authority
DE
Germany
Prior art keywords
cpu
devices
cpus
memory
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69627240T
Other languages
English (en)
Other versions
DE69627240T2 (de
Inventor
David Paul Sonnier
William Patterson Bunton
Cutts, Jr
James Stevens Klecka
John C Krause
William Joel Watson
Linda Ellen Zalzala
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Application granted granted Critical
Publication of DE69627240D1 publication Critical patent/DE69627240D1/de
Publication of DE69627240T2 publication Critical patent/DE69627240T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31727Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12Synchronisation of different clock signals provided by a plurality of clock generators
    • GPHYSICS
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    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
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    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1604Error detection or correction of the data by redundancy in hardware where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
    • GPHYSICS
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    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1629Error detection by comparing the output of redundant processing systems
    • G06F11/1633Error detection by comparing the output of redundant processing systems using mutual exchange of the output between the redundant processing components
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    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1629Error detection by comparing the output of redundant processing systems
    • G06F11/1641Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G06F11/1645Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components and the comparison itself uses redundant hardware
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14Protection against unauthorised use of memory or access to memory
    • G06F12/1458Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G06F12/1483Protection against unauthorised use of memory or access to memory by checking the subject access rights using an access-table, e.g. matrix or list
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/10Flow control; Congestion control
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Buffering arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Buffering arrangements
    • H04L49/901Buffering arrangements using storage descriptor, e.g. read or write pointers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Buffering arrangements
    • H04L49/9057Arrangements for supporting packet reassembly or resequencing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/40Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass for recovering from a failure of a protocol instance or entity, e.g. service redundancy protocols, protocol state redundancy or protocol service redirection
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/004Error avoidance
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1666Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G06F11/167Error detection by comparing the memory output
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1675Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1683Temporal synchronisation or re-synchronisation of redundant processing components at instruction level
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1695Error detection or correction of the data by redundancy in hardware which are operating with time diversity
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2043Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share a common memory address space
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2097Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements maintaining the standby controller/processing unit updated
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/273Tester hardware, i.e. output processing circuits
    • G06F11/2736Tester hardware, i.e. output processing circuits using a dedicated service processor for test
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845Systems in which the redundancy can be transformed in increased performance
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems 
    • H04L12/56Packet switching systems
DE69627240T 1992-12-17 1996-06-06 Synchronisierte Datenübermittlung zwischen Einheiten eines Verarbeitungssystems Expired - Fee Related DE69627240T2 (de)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US99294492A 1992-12-17 1992-12-17
US482628 1995-06-07
US08/473,541 US5751955A (en) 1992-12-17 1995-06-07 Method of synchronizing a pair of central processor units for duplex, lock-step operation by copying data into a corresponding locations of another memory
US08/485,053 US5790776A (en) 1992-12-17 1995-06-07 Apparatus for detecting divergence between a pair of duplexed, synchronized processor elements
US08/484,281 US5838894A (en) 1992-12-17 1995-06-07 Logical, fail-functional, dual central processor units formed from three processor units
US08/485,062 US6496940B1 (en) 1992-12-17 1995-06-07 Multiple processor system with standby sparing
US08/485,055 US6233702B1 (en) 1992-12-17 1995-06-07 Self-checked, lock step processor pairs
US08/483,748 US5689689A (en) 1992-12-17 1995-06-07 Clock circuits for synchronized processor systems having clock generator circuit with a voltage control oscillator producing a clock signal synchronous with a master clock signal
US08/474,770 US5675579A (en) 1992-12-17 1995-06-07 Method for verifying responses to messages using a barrier message
US08/482,628 US5574849A (en) 1992-12-17 1995-06-07 Synchronized data transmission between elements of a processing system
US08/474,772 US5914953A (en) 1992-12-17 1995-06-07 Network message routing using routing table information and supplemental enable information for deadlock prevention

Publications (2)

Publication Number Publication Date
DE69627240D1 true DE69627240D1 (de) 2003-05-15
DE69627240T2 DE69627240T2 (de) 2004-01-08

Family

ID=38982880

Family Applications (7)

Application Number Title Priority Date Filing Date
DE69627750T Expired - Fee Related DE69627750T2 (de) 1992-12-17 1996-06-06 Verfahren zur Divergenzdetektion zwischen einem Paar von synchronisierten Duplexprozessorelementen
DE69627749T Expired - Fee Related DE69627749T2 (de) 1992-12-17 1996-06-06 Verfahren zur Synchronisation zweier zentraler Verarbeitungseinheiten für Duplex-Lock-Step-Operationen
DE69626583T Expired - Fee Related DE69626583T2 (de) 1992-12-17 1996-06-06 Schnellfehlendes, funktionellfehlendes, fehlertolerantes Multiprozessorsystem
DE69626239T Expired - Fee Related DE69626239T2 (de) 1992-12-17 1996-06-06 Fehlertolerantes Multiprozessorsystem
DE69627240T Expired - Fee Related DE69627240T2 (de) 1992-12-17 1996-06-06 Synchronisierte Datenübermittlung zwischen Einheiten eines Verarbeitungssystems
DE69635570T Expired - Fee Related DE69635570T2 (de) 1992-12-17 1996-06-06 Taktschaltung für ein schnellfehlendes, funktionellfehlendes, fehlertolerantes Multiprozessorsystem
DE69629766T Expired - Fee Related DE69629766T2 (de) 1992-12-17 1996-06-06 Schnell versagendes, funktionell versagendes fehlertolerantes Mehrprozessorsystem

Family Applications Before (4)

Application Number Title Priority Date Filing Date
DE69627750T Expired - Fee Related DE69627750T2 (de) 1992-12-17 1996-06-06 Verfahren zur Divergenzdetektion zwischen einem Paar von synchronisierten Duplexprozessorelementen
DE69627749T Expired - Fee Related DE69627749T2 (de) 1992-12-17 1996-06-06 Verfahren zur Synchronisation zweier zentraler Verarbeitungseinheiten für Duplex-Lock-Step-Operationen
DE69626583T Expired - Fee Related DE69626583T2 (de) 1992-12-17 1996-06-06 Schnellfehlendes, funktionellfehlendes, fehlertolerantes Multiprozessorsystem
DE69626239T Expired - Fee Related DE69626239T2 (de) 1992-12-17 1996-06-06 Fehlertolerantes Multiprozessorsystem

Family Applications After (2)

Application Number Title Priority Date Filing Date
DE69635570T Expired - Fee Related DE69635570T2 (de) 1992-12-17 1996-06-06 Taktschaltung für ein schnellfehlendes, funktionellfehlendes, fehlertolerantes Multiprozessorsystem
DE69629766T Expired - Fee Related DE69629766T2 (de) 1992-12-17 1996-06-06 Schnell versagendes, funktionell versagendes fehlertolerantes Mehrprozessorsystem

Country Status (5)

Country Link
US (9) US6233702B1 (de)
EP (9) EP0757318B1 (de)
JP (9) JPH1091587A (de)
CA (9) CA2178409A1 (de)
DE (7) DE69627750T2 (de)

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US5751955A (en) 1998-05-12
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DE69627750D1 (de) 2003-06-05
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US5675579A (en) 1997-10-07
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US5838894A (en) 1998-11-17
US6233702B1 (en) 2001-05-15
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CA2178391A1 (en) 1996-12-08
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