DE69628828D1 - Flächenanordnung für skalierbare mehrlagige verbindungsarchitektur - Google Patents

Flächenanordnung für skalierbare mehrlagige verbindungsarchitektur

Info

Publication number
DE69628828D1
DE69628828D1 DE69628828T DE69628828T DE69628828D1 DE 69628828 D1 DE69628828 D1 DE 69628828D1 DE 69628828 T DE69628828 T DE 69628828T DE 69628828 T DE69628828 T DE 69628828T DE 69628828 D1 DE69628828 D1 DE 69628828D1
Authority
DE
Germany
Prior art keywords
level routing
routing resources
tab
coupling
area arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69628828T
Other languages
English (en)
Inventor
S Ting
M Pani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BTR Inc
Original Assignee
BTR Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BTR Inc filed Critical BTR Inc
Application granted granted Critical
Publication of DE69628828D1 publication Critical patent/DE69628828D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17792—Structural details for adapting physical parameters for operating speed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks
DE69628828T 1995-05-03 1996-04-30 Flächenanordnung für skalierbare mehrlagige verbindungsarchitektur Expired - Lifetime DE69628828D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/434,980 US5850564A (en) 1995-05-03 1995-05-03 Scalable multiple level tab oriented interconnect architecture
PCT/US1996/005982 WO1996035262A1 (en) 1995-05-03 1996-04-30 Floor plan for scalable multiple level interconnect architecture

Publications (1)

Publication Number Publication Date
DE69628828D1 true DE69628828D1 (de) 2003-07-31

Family

ID=23726498

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69628828T Expired - Lifetime DE69628828D1 (de) 1995-05-03 1996-04-30 Flächenanordnung für skalierbare mehrlagige verbindungsarchitektur

Country Status (10)

Country Link
US (4) US5850564A (de)
EP (1) EP0824792B1 (de)
JP (1) JP3684241B2 (de)
KR (1) KR19990008271A (de)
CN (1) CN1124690C (de)
AT (1) ATE243895T1 (de)
AU (1) AU5851596A (de)
DE (1) DE69628828D1 (de)
TW (1) TW289825B (de)
WO (1) WO1996035262A1 (de)

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US6838902B1 (en) 2003-05-28 2005-01-04 Actel Corporation Synchronous first-in/first-out block memory for a field programmable gate array
US7375553B1 (en) 2003-05-28 2008-05-20 Actel Corporation Clock tree network in a field programmable gate array
US6867615B1 (en) 2003-05-30 2005-03-15 Actel Corporation Dedicated input/output first in/first out module for a field programmable gate array
US7373642B2 (en) * 2003-07-29 2008-05-13 Stretch, Inc. Defining instruction extensions in a standard programming language
US7418575B2 (en) * 2003-07-29 2008-08-26 Stretch, Inc. Long instruction word processing with instruction extensions
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US7526632B1 (en) * 2003-10-22 2009-04-28 Stretch, Inc. System, apparatus and method for implementing multifunctional memory in reconfigurable data path processing
US7622947B1 (en) * 2003-12-18 2009-11-24 Nvidia Corporation Redundant circuit presents connections on specified I/O ports
US6975139B2 (en) 2004-03-30 2005-12-13 Advantage Logic, Inc. Scalable non-blocking switching network for programmable logic
US7460529B2 (en) * 2004-07-29 2008-12-02 Advantage Logic, Inc. Interconnection fabric using switching networks in hierarchy
US20060080632A1 (en) * 2004-09-30 2006-04-13 Mathstar, Inc. Integrated circuit layout having rectilinear structure of objects
US20070247189A1 (en) * 2005-01-25 2007-10-25 Mathstar Field programmable semiconductor object array integrated circuit
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EP3480956B1 (de) 2013-03-15 2021-01-06 The Regents of the University of California Netzwerkarchitekturen für grenzenlose hierarchische verbindungen
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Also Published As

Publication number Publication date
EP0824792B1 (de) 2003-06-25
EP0824792A1 (de) 1998-02-25
WO1996035262A1 (en) 1996-11-07
CN1189258A (zh) 1998-07-29
US20060114023A1 (en) 2006-06-01
US20020070756A1 (en) 2002-06-13
CN1124690C (zh) 2003-10-15
KR19990008271A (ko) 1999-01-25
US6417690B1 (en) 2002-07-09
ATE243895T1 (de) 2003-07-15
AU5851596A (en) 1996-11-21
US7009422B2 (en) 2006-03-07
TW289825B (de) 1996-11-01
US7126375B2 (en) 2006-10-24
JPH11505082A (ja) 1999-05-11
JP3684241B2 (ja) 2005-08-17
US5850564A (en) 1998-12-15

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