DE69634227D1 - Emulationssystem mit emulierten Mehrtaktzyklen pro Emulation-Taktzyklus und Signalweglenkung - Google Patents

Emulationssystem mit emulierten Mehrtaktzyklen pro Emulation-Taktzyklus und Signalweglenkung

Info

Publication number
DE69634227D1
DE69634227D1 DE69634227T DE69634227T DE69634227D1 DE 69634227 D1 DE69634227 D1 DE 69634227D1 DE 69634227 T DE69634227 T DE 69634227T DE 69634227 T DE69634227 T DE 69634227T DE 69634227 D1 DE69634227 D1 DE 69634227D1
Authority
DE
Germany
Prior art keywords
emulation
cycles per
signal routing
clock
clock cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69634227T
Other languages
English (en)
Other versions
DE69634227T2 (de
Inventor
Ingo Schaefer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Application granted granted Critical
Publication of DE69634227D1 publication Critical patent/DE69634227D1/de
Publication of DE69634227T2 publication Critical patent/DE69634227T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
DE69634227T 1995-06-28 1996-06-24 Emulationssystem mit emulierten Mehrtaktzyklen pro Emulation-Taktzyklus und Signalweglenkung Expired - Lifetime DE69634227T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/496,239 US5923865A (en) 1995-06-28 1995-06-28 Emulation system having multiple emulated clock cycles per emulator clock cycle and improved signal routing
US496239 1995-06-28

Publications (2)

Publication Number Publication Date
DE69634227D1 true DE69634227D1 (de) 2005-03-03
DE69634227T2 DE69634227T2 (de) 2005-12-29

Family

ID=23971827

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69634227T Expired - Lifetime DE69634227T2 (de) 1995-06-28 1996-06-24 Emulationssystem mit emulierten Mehrtaktzyklen pro Emulation-Taktzyklus und Signalweglenkung

Country Status (4)

Country Link
US (1) US5923865A (de)
EP (1) EP0755016B1 (de)
JP (1) JP3896177B2 (de)
DE (1) DE69634227T2 (de)

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US6141636A (en) * 1997-03-31 2000-10-31 Quickturn Design Systems, Inc. Logic analysis subsystem in a time-sliced emulator
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US7379859B2 (en) * 2001-04-24 2008-05-27 Mentor Graphics Corporation Emulator with switching network connections
US7043417B1 (en) 2000-09-06 2006-05-09 Quickturn Design Systems, Inc. High speed software driven emulator comprised of a plurality of emulation processors with improved multiplexed data memory
US6842728B2 (en) * 2001-03-12 2005-01-11 International Business Machines Corporation Time-multiplexing data between asynchronous clock domains within cycle simulation and emulation environments
US7738399B2 (en) * 2004-06-01 2010-06-15 Quickturn Design Systems Inc. System and method for identifying target systems
US7738398B2 (en) * 2004-06-01 2010-06-15 Quickturn Design Systems, Inc. System and method for configuring communication systems
US7739093B2 (en) * 2004-06-01 2010-06-15 Quickturn Design System, Inc. Method of visualization in processor based emulation system
US7353162B2 (en) * 2005-02-11 2008-04-01 S2C, Inc. Scalable reconfigurable prototyping system and method
US7555424B2 (en) 2006-03-16 2009-06-30 Quickturn Design Systems, Inc. Method and apparatus for rewinding emulated memory circuits
US8595683B1 (en) 2012-04-12 2013-11-26 Cadence Design Systems, Inc. Generating user clocks for a prototyping environment
US11214973B1 (en) 2012-06-15 2022-01-04 Aquastar Pool Products, Inc. Low profile circular drain with water stop for swimming pool and diverter for use therein
US11078681B1 (en) 2012-06-15 2021-08-03 Aquastar Pool Products, Inc. Low profile circular drain with water stop for swimming pool and diverter for use therein
US9540837B2 (en) 2012-06-15 2017-01-10 Olaf Mjelde Low profile circular drain with water stop for swimming pools
US10949588B1 (en) * 2016-11-10 2021-03-16 Synopsys, Inc. High speed, low hardware footprint waveform
US10796048B1 (en) * 2017-06-16 2020-10-06 Synopsys, Inc. Adding delay elements to enable mapping a time division multiplexing circuit on an FPGA of a hardware emulator
US10934730B2 (en) 2018-01-15 2021-03-02 Hayward Industries, Inc. In-floor swimming pool drain and sump assembly

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US5475830A (en) * 1992-01-31 1995-12-12 Quickturn Design Systems, Inc. Structure and method for providing a reconfigurable emulation circuit without hold time violations
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US5572710A (en) * 1992-09-11 1996-11-05 Kabushiki Kaisha Toshiba High speed logic simulation system using time division emulation suitable for large scale logic circuits
US5425036A (en) * 1992-09-18 1995-06-13 Quickturn Design Systems, Inc. Method and apparatus for debugging reconfigurable emulation systems
US5452239A (en) * 1993-01-29 1995-09-19 Quickturn Design Systems, Inc. Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system
US5596742A (en) * 1993-04-02 1997-01-21 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5448522A (en) * 1994-03-24 1995-09-05 Quickturn Design Systems, Inc. Multi-port memory emulation using tag registers
US5551013A (en) * 1994-06-03 1996-08-27 International Business Machines Corporation Multiprocessor for hardware emulation

Also Published As

Publication number Publication date
EP0755016A2 (de) 1997-01-22
DE69634227T2 (de) 2005-12-29
EP0755016A3 (de) 2000-09-13
JPH09101975A (ja) 1997-04-15
JP3896177B2 (ja) 2007-03-22
US5923865A (en) 1999-07-13
EP0755016B1 (de) 2005-01-26

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