DE69635187D1 - Schaltungsanordnung zur taktsignalreinigung - Google Patents

Schaltungsanordnung zur taktsignalreinigung

Info

Publication number
DE69635187D1
DE69635187D1 DE69635187T DE69635187T DE69635187D1 DE 69635187 D1 DE69635187 D1 DE 69635187D1 DE 69635187 T DE69635187 T DE 69635187T DE 69635187 T DE69635187 T DE 69635187T DE 69635187 D1 DE69635187 D1 DE 69635187D1
Authority
DE
Germany
Prior art keywords
clock signal
circuit arrangement
signal cleaning
cleaning
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69635187T
Other languages
English (en)
Other versions
DE69635187T2 (de
Inventor
Evan Arkas
Nicholas Arkas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Intelligence Inc
Original Assignee
Advanced Intelligence Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Intelligence Inc filed Critical Advanced Intelligence Inc
Publication of DE69635187D1 publication Critical patent/DE69635187D1/de
Application granted granted Critical
Publication of DE69635187T2 publication Critical patent/DE69635187T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
DE69635187T 1995-11-02 1996-10-24 Schaltungsanordnung zur taktsignalreinigung Expired - Fee Related DE69635187T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CA2161982 1995-11-02
CA002161982A CA2161982A1 (en) 1995-11-02 1995-11-02 Clock cleaner
PCT/CA1996/000706 WO1997016901A1 (en) 1995-11-02 1996-10-24 Clock signal cleaning circuit

Publications (2)

Publication Number Publication Date
DE69635187D1 true DE69635187D1 (de) 2005-10-20
DE69635187T2 DE69635187T2 (de) 2006-07-06

Family

ID=4156897

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69635187T Expired - Fee Related DE69635187T2 (de) 1995-11-02 1996-10-24 Schaltungsanordnung zur taktsignalreinigung

Country Status (6)

Country Link
US (1) US6246276B1 (de)
EP (1) EP0858699B1 (de)
CA (1) CA2161982A1 (de)
DE (1) DE69635187T2 (de)
ES (1) ES2249787T3 (de)
WO (1) WO1997016901A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3703997B2 (ja) * 1999-07-06 2005-10-05 沖電気工業株式会社 映像信号制御回路
US6566939B1 (en) * 2001-08-06 2003-05-20 Lsi Logic Corporation Programmable glitch filter
US7375569B2 (en) * 2005-09-21 2008-05-20 Leco Corporation Last stage synchronizer system
US7420399B2 (en) * 2005-11-10 2008-09-02 Jonghee Han Duty cycle corrector
US8294502B2 (en) * 2011-03-04 2012-10-23 Altera Corporation Delay circuitry

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1550432A (de) * 1967-11-08 1968-12-20
JPH0624315B2 (ja) * 1983-11-04 1994-03-30 日本ビクター株式会社 移相器
US4805197A (en) * 1986-12-18 1989-02-14 Lecroy Corporation Method and apparatus for recovering clock information from a received digital signal and for synchronizing that signal
EP0476968A3 (en) 1990-09-21 1992-11-25 Ncr Corporation Clock recovery circuit
US5349612A (en) * 1992-06-19 1994-09-20 Advanced Micro Devices, Inc. Digital serializer and time delay regulator

Also Published As

Publication number Publication date
ES2249787T3 (es) 2006-04-01
WO1997016901A1 (en) 1997-05-09
EP0858699B1 (de) 2005-09-14
CA2161982A1 (en) 1997-05-03
EP0858699A1 (de) 1998-08-19
US6246276B1 (en) 2001-06-12
DE69635187T2 (de) 2006-07-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee