DE69635431D1 - Verbindungsarchitektur für programmierbare logische Vorrichtung mit grobkörniger Oberflächenstruktur - Google Patents

Verbindungsarchitektur für programmierbare logische Vorrichtung mit grobkörniger Oberflächenstruktur

Info

Publication number
DE69635431D1
DE69635431D1 DE69635431T DE69635431T DE69635431D1 DE 69635431 D1 DE69635431 D1 DE 69635431D1 DE 69635431 T DE69635431 T DE 69635431T DE 69635431 T DE69635431 T DE 69635431T DE 69635431 D1 DE69635431 D1 DE 69635431D1
Authority
DE
Germany
Prior art keywords
coarse
programmable logic
logic device
surface structure
grained surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69635431T
Other languages
English (en)
Other versions
DE69635431T2 (de
Inventor
Richard G Cliff
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Publication of DE69635431D1 publication Critical patent/DE69635431D1/de
Application granted granted Critical
Publication of DE69635431T2 publication Critical patent/DE69635431T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
DE69635431T 1995-06-07 1996-05-31 Verbindungsarchitektur für programmierbare logische Vorrichtung mit grobkörniger Oberflächenstruktur Expired - Lifetime DE69635431T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/484,831 US5815726A (en) 1994-11-04 1995-06-07 Coarse-grained look-up table architecture
US484831 1995-06-07

Publications (2)

Publication Number Publication Date
DE69635431D1 true DE69635431D1 (de) 2005-12-22
DE69635431T2 DE69635431T2 (de) 2006-06-22

Family

ID=23925801

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69635431T Expired - Lifetime DE69635431T2 (de) 1995-06-07 1996-05-31 Verbindungsarchitektur für programmierbare logische Vorrichtung mit grobkörniger Oberflächenstruktur
DE69637399T Expired - Lifetime DE69637399T2 (de) 1995-06-07 1996-05-31 Grobkörnig strukturierte integrierte Halbleiterschaltung mit Nachschlagtabellen

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE69637399T Expired - Lifetime DE69637399T2 (de) 1995-06-07 1996-05-31 Grobkörnig strukturierte integrierte Halbleiterschaltung mit Nachschlagtabellen

Country Status (3)

Country Link
US (2) US5815726A (de)
EP (2) EP1659693B1 (de)
DE (2) DE69635431T2 (de)

Families Citing this family (173)

* Cited by examiner, † Cited by third party
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US6122720A (en) 2000-09-19
EP1659693A3 (de) 2006-07-19
DE69637399T2 (de) 2008-12-18
EP0748049B1 (de) 2005-11-16
DE69635431T2 (de) 2006-06-22
US5815726A (en) 1998-09-29
EP1659693B1 (de) 2008-01-02
EP1659693A2 (de) 2006-05-24
EP0748049A3 (de) 1997-11-19
DE69637399D1 (de) 2008-02-14

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