DE69706873T2 - Löschverfahren für mehrere-bits-pro-zelle flash -eeprom mit seitenmodus - Google Patents

Löschverfahren für mehrere-bits-pro-zelle flash -eeprom mit seitenmodus

Info

Publication number
DE69706873T2
DE69706873T2 DE69706873T DE69706873T DE69706873T2 DE 69706873 T2 DE69706873 T2 DE 69706873T2 DE 69706873 T DE69706873 T DE 69706873T DE 69706873 T DE69706873 T DE 69706873T DE 69706873 T2 DE69706873 T2 DE 69706873T2
Authority
DE
Germany
Prior art keywords
flash eeprom
multiple bits
side mode
cell flash
erase procedure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69706873T
Other languages
English (en)
Other versions
DE69706873D1 (de
Inventor
Colin Bill
Jonathan Su
Prakash Gutala
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69706873D1 publication Critical patent/DE69706873D1/de
Application granted granted Critical
Publication of DE69706873T2 publication Critical patent/DE69706873T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628Programming or writing circuits; Data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628Programming or writing circuits; Data input circuits
    • G11C11/5635Erasing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562Multilevel memory programming aspects
    • G11C2211/5621Multilevel programming verification
DE69706873T 1996-08-22 1997-04-16 Löschverfahren für mehrere-bits-pro-zelle flash -eeprom mit seitenmodus Expired - Fee Related DE69706873T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/701,288 US5675537A (en) 1996-08-22 1996-08-22 Erase method for page mode multiple bits-per-cell flash EEPROM
PCT/US1997/006414 WO1998008225A1 (en) 1996-08-22 1997-04-16 Erase method for page mode multiple bits-per-cell flash eeprom

Publications (2)

Publication Number Publication Date
DE69706873D1 DE69706873D1 (de) 2001-10-25
DE69706873T2 true DE69706873T2 (de) 2002-06-13

Family

ID=24816766

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69706873T Expired - Fee Related DE69706873T2 (de) 1996-08-22 1997-04-16 Löschverfahren für mehrere-bits-pro-zelle flash -eeprom mit seitenmodus

Country Status (5)

Country Link
US (1) US5675537A (de)
EP (1) EP0922285B1 (de)
DE (1) DE69706873T2 (de)
TW (1) TW334568B (de)
WO (1) WO1998008225A1 (de)

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US5928370A (en) * 1997-02-05 1999-07-27 Lexar Media, Inc. Method and apparatus for verifying erasure of memory blocks within a non-volatile memory structure
US6252799B1 (en) * 1997-04-11 2001-06-26 Programmable Silicon Solutions Device with embedded flash and EEPROM memories
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KR100297874B1 (ko) 1997-09-08 2001-10-24 윤종용 강유전체랜덤액세스메모리장치
US5909449A (en) * 1997-09-08 1999-06-01 Invox Technology Multibit-per-cell non-volatile memory with error detection and correction
KR100339024B1 (ko) * 1998-03-28 2002-09-18 주식회사 하이닉스반도체 플래쉬메모리장치의센스앰프회로
EP0978844B1 (de) * 1998-08-07 2005-11-02 STMicroelectronics S.r.l. Ausleseanordnung für Multibit-Halbleiterspeicheranordnung
US6185128B1 (en) * 1999-10-19 2001-02-06 Advanced Micro Devices, Inc. Reference cell four-way switch for a simultaneous operation flash memory device
FR2801419B1 (fr) 1999-11-18 2003-07-25 St Microelectronics Sa Procede et dispositif de lecture pour memoire en circuit integre
US6304486B1 (en) * 1999-12-20 2001-10-16 Fujitsu Limited Sensing time control device and method
US6243300B1 (en) 2000-02-16 2001-06-05 Advanced Micro Devices, Inc. Substrate hole injection for neutralizing spillover charge generated during programming of a non-volatile memory cell
US6215702B1 (en) 2000-02-16 2001-04-10 Advanced Micro Devices, Inc. Method of maintaining constant erasing speeds for non-volatile memory cells
US6266281B1 (en) 2000-02-16 2001-07-24 Advanced Micro Devices, Inc. Method of erasing non-volatile memory cells
US6477083B1 (en) 2000-10-11 2002-11-05 Advanced Micro Devices, Inc. Select transistor architecture for a virtual ground non-volatile memory cell array
US6583479B1 (en) 2000-10-16 2003-06-24 Advanced Micro Devices, Inc. Sidewall NROM and method of manufacture thereof for non-volatile memory cells
US6563741B2 (en) 2001-01-30 2003-05-13 Micron Technology, Inc. Flash memory device and method of erasing
US6344994B1 (en) 2001-01-31 2002-02-05 Advanced Micro Devices Data retention characteristics as a result of high temperature bake
US6493261B1 (en) 2001-01-31 2002-12-10 Advanced Micro Devices, Inc. Single bit array edges
US6307784B1 (en) 2001-02-28 2001-10-23 Advanced Micro Devices Negative gate erase
US6456533B1 (en) 2001-02-28 2002-09-24 Advanced Micro Devices, Inc. Higher program VT and faster programming rates based on improved erase methods
US6442074B1 (en) 2001-02-28 2002-08-27 Advanced Micro Devices, Inc. Tailored erase method using higher program VT and higher negative gate erase
US6584017B2 (en) * 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US6906951B2 (en) * 2001-06-14 2005-06-14 Multi Level Memory Technology Bit line reference circuits for binary and multiple-bit-per-cell memories
US6512701B1 (en) 2001-06-21 2003-01-28 Advanced Micro Devices, Inc. Erase method for dual bit virtual ground flash
US7057935B2 (en) * 2001-08-30 2006-06-06 Micron Technology, Inc. Erase verify for non-volatile memory
DE10297641T5 (de) * 2002-01-16 2005-01-05 Advanced Micro Devices, Inc., Sunnyvale Ladungsinjektion
US6842381B2 (en) * 2002-01-25 2005-01-11 Taiwan Semiconductor Manufacturing Co. Method of marginal erasure for the testing of flash memories
US6700815B2 (en) * 2002-04-08 2004-03-02 Advanced Micro Devices, Inc. Refresh scheme for dynamic page programming
US6711062B1 (en) 2002-07-17 2004-03-23 Taiwan Semiconductor Manufacturing Company Erase method of split gate flash memory reference cells
JP3935139B2 (ja) 2002-11-29 2007-06-20 株式会社東芝 半導体記憶装置
US6898680B2 (en) * 2003-01-03 2005-05-24 Micrel, Incorporated Minimization of overhead of non-volatile memory operation
US6735114B1 (en) * 2003-02-04 2004-05-11 Advanced Micro Devices, Inc. Method of improving dynamic reference tracking for flash memory unit
JP2004348803A (ja) * 2003-05-20 2004-12-09 Sharp Corp 不揮発性メモリ素子のプログラム検証方法および半導体記憶装置とそれを備えた携帯電子機器
US7023735B2 (en) * 2003-06-17 2006-04-04 Ramot At Tel-Aviv University Ltd. Methods of increasing the reliability of a flash memory
US7324374B2 (en) * 2003-06-20 2008-01-29 Spansion Llc Memory with a core-based virtual ground and dynamic reference sensing scheme
US6975535B2 (en) * 2003-08-14 2005-12-13 Mosel Vitelic, Inc. Electronic memory, such as flash EPROM, with bitwise-adjusted writing current or/and voltage
US7173852B2 (en) * 2003-10-03 2007-02-06 Sandisk Corporation Corrected data storage and handling methods
US7012835B2 (en) * 2003-10-03 2006-03-14 Sandisk Corporation Flash memory data correction and scrub techniques
US7307884B2 (en) 2004-06-15 2007-12-11 Sandisk Corporation Concurrent programming of non-volatile memory
US7352618B2 (en) * 2004-12-15 2008-04-01 Samsung Electronics Co., Ltd. Multi-level cell memory device and associated read method
US7395404B2 (en) * 2004-12-16 2008-07-01 Sandisk Corporation Cluster auto-alignment for storing addressable data packets in a non-volatile memory array
US7315916B2 (en) * 2004-12-16 2008-01-01 Sandisk Corporation Scratch pad block
JP4336342B2 (ja) * 2005-12-16 2009-09-30 シャープ株式会社 不揮発性半導体記憶装置
US7701779B2 (en) * 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US7886204B2 (en) 2006-09-27 2011-02-08 Sandisk Corporation Methods of cell population distribution assisted read margining
US7716538B2 (en) * 2006-09-27 2010-05-11 Sandisk Corporation Memory with cell population distribution assisted read margining
US7477547B2 (en) * 2007-03-28 2009-01-13 Sandisk Corporation Flash memory refresh techniques triggered by controlled scrub data reads
US7573773B2 (en) * 2007-03-28 2009-08-11 Sandisk Corporation Flash memory with data refresh triggered by controlled scrub data reads
US7787282B2 (en) * 2008-03-21 2010-08-31 Micron Technology, Inc. Sensing resistance variable memory
US8130528B2 (en) 2008-08-25 2012-03-06 Sandisk 3D Llc Memory system with sectional data lines
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US8687421B2 (en) 2011-11-21 2014-04-01 Sandisk Technologies Inc. Scrub techniques for use with dynamic read
US9230689B2 (en) 2014-03-17 2016-01-05 Sandisk Technologies Inc. Finding read disturbs on non-volatile memories
US9552171B2 (en) 2014-10-29 2017-01-24 Sandisk Technologies Llc Read scrub with adaptive counter management
US9978456B2 (en) 2014-11-17 2018-05-22 Sandisk Technologies Llc Techniques for reducing read disturb in partially written blocks of non-volatile memory
US9349479B1 (en) 2014-11-18 2016-05-24 Sandisk Technologies Inc. Boundary word line operation in nonvolatile memory
US9449700B2 (en) 2015-02-13 2016-09-20 Sandisk Technologies Llc Boundary word line search and open block read methods with reduced read disturb
US9653154B2 (en) 2015-09-21 2017-05-16 Sandisk Technologies Llc Write abort detection for multi-state memories
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Also Published As

Publication number Publication date
WO1998008225A1 (en) 1998-02-26
TW334568B (en) 1998-06-21
EP0922285A1 (de) 1999-06-16
DE69706873D1 (de) 2001-10-25
US5675537A (en) 1997-10-07
EP0922285B1 (de) 2001-09-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee