DE69714507T2 - Einrichtung und Verfahren zur On-line-Überwachung von Speichern - Google Patents

Einrichtung und Verfahren zur On-line-Überwachung von Speichern

Info

Publication number
DE69714507T2
DE69714507T2 DE69714507T DE69714507T DE69714507T2 DE 69714507 T2 DE69714507 T2 DE 69714507T2 DE 69714507 T DE69714507 T DE 69714507T DE 69714507 T DE69714507 T DE 69714507T DE 69714507 T2 DE69714507 T2 DE 69714507T2
Authority
DE
Germany
Prior art keywords
memory
alert
nature
performance
correction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69714507T
Other languages
English (en)
Other versions
DE69714507D1 (de
Inventor
Ji Zhu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of DE69714507D1 publication Critical patent/DE69714507D1/de
Application granted granted Critical
Publication of DE69714507T2 publication Critical patent/DE69714507T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/106Correcting systematically all correctable errors, i.e. scrubbing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751Error or fault detection not based on redundancy
    • G06F11/0754Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/81Threshold
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/865Monitoring of software
DE69714507T 1996-05-10 1997-04-28 Einrichtung und Verfahren zur On-line-Überwachung von Speichern Expired - Fee Related DE69714507T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/644,314 US5974576A (en) 1996-05-10 1996-05-10 On-line memory monitoring system and methods

Publications (2)

Publication Number Publication Date
DE69714507D1 DE69714507D1 (de) 2002-09-12
DE69714507T2 true DE69714507T2 (de) 2003-04-24

Family

ID=24584376

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69714507T Expired - Fee Related DE69714507T2 (de) 1996-05-10 1997-04-28 Einrichtung und Verfahren zur On-line-Überwachung von Speichern

Country Status (4)

Country Link
US (1) US5974576A (de)
EP (1) EP0806726B1 (de)
JP (1) JPH1055320A (de)
DE (1) DE69714507T2 (de)

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DE102020216072A1 (de) 2020-12-16 2022-06-23 Infineon Technologies Ag Vorrichtung und Verfahren zum Bearbeiten von Bitfolgen

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US6701480B1 (en) * 2000-03-08 2004-03-02 Rockwell Automation Technologies, Inc. System and method for providing error check and correction in memory systems
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US7168010B2 (en) * 2002-08-12 2007-01-23 Intel Corporation Various methods and apparatuses to track failing memory locations to enable implementations for invalidating repeatedly failing memory locations
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JP4261462B2 (ja) * 2004-11-05 2009-04-30 株式会社東芝 不揮発性メモリシステム
US20070011513A1 (en) * 2005-06-13 2007-01-11 Intel Corporation Selective activation of error mitigation based on bit level error count
US7904760B2 (en) * 2005-07-06 2011-03-08 Cisco Technology, Inc. Method and system for using presence information in error notification
JP5283845B2 (ja) * 2007-02-07 2013-09-04 株式会社メガチップス ビットエラーの予防方法、情報処理装置
JP2008269473A (ja) * 2007-04-24 2008-11-06 Toshiba Corp データ残存期間管理装置及び方法
JP5082580B2 (ja) * 2007-05-15 2012-11-28 富士通株式会社 メモリシステム、メモリコントローラ、制御方法及び制御プログラム
US8140908B2 (en) * 2007-06-22 2012-03-20 Microsoft Corporation System and method of client side analysis for identifying failing RAM after a user mode or kernel mode exception
US8468422B2 (en) 2007-12-21 2013-06-18 Oracle America, Inc. Prediction and prevention of uncorrectable memory errors
US20090217281A1 (en) * 2008-02-22 2009-08-27 John M Borkenhagen Adaptable Redundant Bit Steering for DRAM Memory Failures
US20100163756A1 (en) * 2008-12-31 2010-07-01 Custom Test Systems, Llc. Single event upset (SEU) testing system and method
US8230255B2 (en) 2009-12-15 2012-07-24 International Business Machines Corporation Blocking write acces to memory modules of a solid state drive
US8560927B1 (en) 2010-08-26 2013-10-15 Altera Corporation Memory error detection circuitry
CN102467417B (zh) 2010-11-19 2014-04-23 英业达股份有限公司 计算机系统
US9749211B2 (en) 2011-02-15 2017-08-29 Entit Software Llc Detecting network-application service failures
JP5691928B2 (ja) 2011-08-05 2015-04-01 富士通株式会社 プラグインカード収容装置
EP3712774B1 (de) 2011-09-30 2023-02-15 Tahoe Research, Ltd. Vorrichtung und verfahren zur implementierung einer mehrstufigen speicherhierarchie
CN107608910B (zh) 2011-09-30 2021-07-02 英特尔公司 用于实现具有不同操作模式的多级存储器分级结构的设备和方法
US9378133B2 (en) 2011-09-30 2016-06-28 Intel Corporation Autonomous initialization of non-volatile random access memory in a computer system
WO2013048491A1 (en) 2011-09-30 2013-04-04 Intel Corporation Apparatus, method and system that stores bios in non-volatile random access memory
WO2013048493A1 (en) 2011-09-30 2013-04-04 Intel Corporation Memory channel that supports near memory and far memory access
US9317429B2 (en) 2011-09-30 2016-04-19 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy over common memory channels
CN103946813B (zh) * 2011-09-30 2017-08-25 英特尔公司 基于使用统计量追踪的远存储器访问信号的生成
EP3346386B1 (de) 2011-09-30 2020-01-22 Intel Corporation Nichtflüchtiger direktzugriffsspeicher (nvram) als ersatz für herkömmlichen massenspeicher
US8819379B2 (en) 2011-11-15 2014-08-26 Memory Technologies Llc Allocating memory based on performance ranking
US8615724B2 (en) * 2011-12-29 2013-12-24 Flextronics Ap Llc Circuit assembly yield prediction with respect to form factor
JP5781003B2 (ja) * 2012-04-26 2015-09-16 三菱電機株式会社 誤り検出訂正装置およびこれを備えた電子機器
US9232630B1 (en) 2012-05-18 2016-01-05 Flextronics Ap, Llc Method of making an inlay PCB with embedded coin
US9521754B1 (en) 2013-08-19 2016-12-13 Multek Technologies Limited Embedded components in a substrate
US9565748B2 (en) 2013-10-28 2017-02-07 Flextronics Ap, Llc Nano-copper solder for filling thermal vias
JP6866785B2 (ja) 2017-06-29 2021-04-28 富士通株式会社 プロセッサおよびメモリアクセス方法
KR102413096B1 (ko) * 2018-01-08 2022-06-27 삼성전자주식회사 전자 장치 및 그 제어 방법

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102020216072A1 (de) 2020-12-16 2022-06-23 Infineon Technologies Ag Vorrichtung und Verfahren zum Bearbeiten von Bitfolgen

Also Published As

Publication number Publication date
EP0806726A1 (de) 1997-11-12
DE69714507D1 (de) 2002-09-12
EP0806726B1 (de) 2002-08-07
US5974576A (en) 1999-10-26
JPH1055320A (ja) 1998-02-24

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