DE69722138D1 - Code-Optimierer für Pipeline-Rechner - Google Patents
Code-Optimierer für Pipeline-RechnerInfo
- Publication number
- DE69722138D1 DE69722138D1 DE69722138T DE69722138T DE69722138D1 DE 69722138 D1 DE69722138 D1 DE 69722138D1 DE 69722138 T DE69722138 T DE 69722138T DE 69722138 T DE69722138 T DE 69722138T DE 69722138 D1 DE69722138 D1 DE 69722138D1
- Authority
- DE
- Germany
- Prior art keywords
- code optimizer
- computers
- pipeline
- pipeline computers
- optimizer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/44—Encoding
- G06F8/445—Exploiting fine grain parallelism, i.e. parallelism at instruction level
- G06F8/4452—Software pipelining
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/752,683 US5930510A (en) | 1996-11-19 | 1996-11-19 | Method and apparatus for an improved code optimizer for pipelined computers |
US752683 | 1996-11-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69722138D1 true DE69722138D1 (de) | 2003-06-26 |
DE69722138T2 DE69722138T2 (de) | 2004-04-08 |
Family
ID=25027339
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69722138T Expired - Fee Related DE69722138T2 (de) | 1996-11-19 | 1997-11-11 | Code-Optimierer für Pipeline-Rechner |
Country Status (4)
Country | Link |
---|---|
US (1) | US5930510A (de) |
EP (2) | EP0843258A3 (de) |
JP (1) | JPH10161884A (de) |
DE (1) | DE69722138T2 (de) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6035125A (en) * | 1997-07-25 | 2000-03-07 | International Business Machines Corporation | Method and system for generating compact code for the loop unrolling transformation |
WO1999012094A1 (de) * | 1997-09-01 | 1999-03-11 | Siemens Nixdorf Informationssysteme Ag | Verfahren zum umsetzen eines objektcodes in einen programmcode |
US6253373B1 (en) * | 1997-10-07 | 2001-06-26 | Hewlett-Packard Company | Tracking loop entry and exit points in a compiler |
US6341370B1 (en) * | 1998-04-24 | 2002-01-22 | Sun Microsystems, Inc. | Integration of data prefetching and modulo scheduling using postpass prefetch insertion |
US6305014B1 (en) * | 1998-06-18 | 2001-10-16 | International Business Machines Corporation | Lifetime-sensitive instruction scheduling mechanism and method |
US6609088B1 (en) * | 1998-07-24 | 2003-08-19 | Interuniversitaire Micro-Elektronica Centrum | Method for determining an optimized memory organization of a digital device |
US6671878B1 (en) * | 2000-03-24 | 2003-12-30 | Brian E. Bliss | Modulo scheduling via binary search for minimum acceptable initiation interval method and apparatus |
US7503033B2 (en) * | 2000-04-28 | 2009-03-10 | Microsoft Corporation | Model for business workflow processes |
US7774219B1 (en) * | 2000-04-28 | 2010-08-10 | Microsoft Corporation | Long running transaction integration with selective dehydration and selective compensation |
US7234126B2 (en) * | 2000-08-23 | 2007-06-19 | Interuniversitair Microelektronica Centrum | Task concurrency management design method |
US6658656B1 (en) * | 2000-10-31 | 2003-12-02 | Hewlett-Packard Development Company, L.P. | Method and apparatus for creating alternative versions of code segments and dynamically substituting execution of the alternative code versions |
US6912709B2 (en) * | 2000-12-29 | 2005-06-28 | Intel Corporation | Mechanism to avoid explicit prologs in software pipelined do-while loops |
JP2003005980A (ja) * | 2001-06-22 | 2003-01-10 | Matsushita Electric Ind Co Ltd | コンパイル装置およびコンパイルプログラム |
US7203942B2 (en) | 2001-09-25 | 2007-04-10 | Interuniversitair Microelektronica Centrum | Method for operating a real-time multimedia terminal in a QoS manner |
GB2380825B (en) * | 2001-10-12 | 2004-07-14 | Siroyan Ltd | Processors and compiling methods for processors |
US7257808B2 (en) * | 2002-01-03 | 2007-08-14 | Intel Corporation | System and method to reduce the size of source code in a processing system |
US7000137B2 (en) * | 2002-10-07 | 2006-02-14 | Hewlett-Packard Development Company, L.P. | System for and method of clock cycle-time analysis using mode-slicing mechanism |
US7096438B2 (en) * | 2002-10-07 | 2006-08-22 | Hewlett-Packard Development Company, L.P. | Method of using clock cycle-time in determining loop schedules during circuit design |
US6983456B2 (en) * | 2002-10-31 | 2006-01-03 | Src Computers, Inc. | Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms |
US7454747B2 (en) * | 2003-02-07 | 2008-11-18 | Sun Microsystems, Inc. | Determining maximum acceptable scheduling load latency using hierarchical search |
US7395419B1 (en) * | 2004-04-23 | 2008-07-01 | Apple Inc. | Macroscalar processor architecture |
US7617496B2 (en) | 2004-04-23 | 2009-11-10 | Apple Inc. | Macroscalar processor architecture |
US7814468B1 (en) * | 2005-04-20 | 2010-10-12 | Oracle America, Inc. | Method for loop reformulation |
US7546592B2 (en) * | 2005-07-21 | 2009-06-09 | International Business Machines Corporation | System and method for optimized swing modulo scheduling based on identification of constrained resources |
US8341615B2 (en) * | 2008-07-11 | 2012-12-25 | International Business Machines Corporation | Single instruction multiple data (SIMD) code generation for parallel loops using versioning and scheduling |
KR20100046877A (ko) * | 2008-10-28 | 2010-05-07 | 삼성전자주식회사 | 언롤 루프에 대한 레지스터 스필을 줄이는 컴파일러 및 그 방법 |
WO2011080054A1 (en) * | 2009-12-30 | 2011-07-07 | International Business Machines Corporation | Extraction of data parallelism |
US9696995B2 (en) | 2009-12-30 | 2017-07-04 | International Business Machines Corporation | Parallel execution unit that extracts data parallelism at runtime |
US8572359B2 (en) | 2009-12-30 | 2013-10-29 | International Business Machines Corporation | Runtime extraction of data parallelism |
US8495607B2 (en) * | 2010-03-01 | 2013-07-23 | International Business Machines Corporation | Performing aggressive code optimization with an ability to rollback changes made by the aggressive optimizations |
US8683185B2 (en) | 2010-07-26 | 2014-03-25 | International Business Machines Corporation | Ceasing parallel processing of first set of loops upon selectable number of monitored terminations and processing second set |
US9329867B2 (en) * | 2014-01-08 | 2016-05-03 | Qualcomm Incorporated | Register allocation for vectors |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04211830A (ja) * | 1990-02-05 | 1992-08-03 | Matsushita Electric Ind Co Ltd | 並列化コンパイル方式 |
US5551039A (en) * | 1992-02-03 | 1996-08-27 | Thinking Machines Corporation | Compiling a source code vector instruction by generating a subgrid loop for iteratively processing array elements by plural processing elements |
US5448737A (en) * | 1992-03-17 | 1995-09-05 | International Business Machines Corporation | System and method for optimizing computer code using a compact data flow representation |
US5491823A (en) * | 1994-01-25 | 1996-02-13 | Silicon Graphics, Inc. | Loop scheduler |
US5659754A (en) * | 1995-03-31 | 1997-08-19 | Sun Microsystems, Inc. | Method and apparatus for an improved optimizing compiler |
US5761514A (en) * | 1995-08-31 | 1998-06-02 | International Business Machines Corporation | Register allocation method and apparatus for truncating runaway lifetimes of program variables in a computer system |
US5809308A (en) * | 1995-11-17 | 1998-09-15 | Sun Microsystems, Inc. | Method and apparatus for efficient determination of an RMII vector for modulo scheduled loops in an optimizing compiler |
US5664193A (en) * | 1995-11-17 | 1997-09-02 | Sun Microsystems, Inc. | Method and apparatus for automatic selection of the load latency to be used in modulo scheduling in an optimizing compiler |
US5835776A (en) * | 1995-11-17 | 1998-11-10 | Sun Microsystems, Inc. | Method and apparatus for instruction scheduling in an optimizing compiler for minimizing overhead instructions |
US5867711A (en) * | 1995-11-17 | 1999-02-02 | Sun Microsystems, Inc. | Method and apparatus for time-reversed instruction scheduling with modulo constraints in an optimizing compiler |
US5768596A (en) * | 1996-04-23 | 1998-06-16 | Silicon Graphics, Inc. | System and method to efficiently represent aliases and indirect memory operations in static single assignment form during compilation |
-
1996
- 1996-11-19 US US08/752,683 patent/US5930510A/en not_active Expired - Lifetime
-
1997
- 1997-11-11 EP EP97309065A patent/EP0843258A3/de not_active Withdrawn
- 1997-11-11 DE DE69722138T patent/DE69722138T2/de not_active Expired - Fee Related
- 1997-11-11 EP EP97309064A patent/EP0843257B1/de not_active Expired - Lifetime
- 1997-11-19 JP JP9318777A patent/JPH10161884A/ja not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
JPH10161884A (ja) | 1998-06-19 |
US5930510A (en) | 1999-07-27 |
EP0843258A3 (de) | 1999-05-12 |
EP0843258A2 (de) | 1998-05-20 |
EP0843257A3 (de) | 1999-05-19 |
DE69722138T2 (de) | 2004-04-08 |
EP0843257B1 (de) | 2003-05-21 |
EP0843257A2 (de) | 1998-05-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |