DE69725632D1 - Halbleiterspeicheranordnung mit "Pipeline" Betrieb - Google Patents

Halbleiterspeicheranordnung mit "Pipeline" Betrieb

Info

Publication number
DE69725632D1
DE69725632D1 DE69725632T DE69725632T DE69725632D1 DE 69725632 D1 DE69725632 D1 DE 69725632D1 DE 69725632 T DE69725632 T DE 69725632T DE 69725632 T DE69725632 T DE 69725632T DE 69725632 D1 DE69725632 D1 DE 69725632D1
Authority
DE
Germany
Prior art keywords
pipeline
semiconductor memory
memory arrangement
arrangement
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69725632T
Other languages
English (en)
Other versions
DE69725632T2 (de
Inventor
Yoshinori Okajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69725632D1 publication Critical patent/DE69725632D1/de
Publication of DE69725632T2 publication Critical patent/DE69725632T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
DE69725632T 1996-02-02 1997-01-30 Halbleiterspeicheranordnung mit "Pipeline" Betrieb Expired - Lifetime DE69725632T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1799096 1996-02-02
JP01799096A JP4084428B2 (ja) 1996-02-02 1996-02-02 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69725632D1 true DE69725632D1 (de) 2003-11-27
DE69725632T2 DE69725632T2 (de) 2004-06-17

Family

ID=11959169

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69725632T Expired - Lifetime DE69725632T2 (de) 1996-02-02 1997-01-30 Halbleiterspeicheranordnung mit "Pipeline" Betrieb

Country Status (6)

Country Link
US (3) US6163832A (de)
EP (1) EP0788110B1 (de)
JP (1) JP4084428B2 (de)
KR (1) KR100267962B1 (de)
DE (1) DE69725632T2 (de)
TW (1) TW332294B (de)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6385645B1 (en) * 1995-08-04 2002-05-07 Belle Gate Investments B.V. Data exchange system comprising portable data processing units
US6230245B1 (en) 1997-02-11 2001-05-08 Micron Technology, Inc. Method and apparatus for generating a variable sequence of memory device command signals
US6175894B1 (en) 1997-03-05 2001-01-16 Micron Technology, Inc. Memory device command buffer apparatus and method and memory devices and computer systems using same
US5996043A (en) 1997-06-13 1999-11-30 Micron Technology, Inc. Two step memory device command buffer apparatus and method and memory devices and computer systems using same
US6484244B1 (en) 1997-06-17 2002-11-19 Micron Technology, Inc. Method and system for storing and processing multiple memory commands
US6286062B1 (en) 1997-07-01 2001-09-04 Micron Technology, Inc. Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus
US6347354B1 (en) * 1997-10-10 2002-02-12 Rambus Incorporated Apparatus and method for maximizing information transfers over limited interconnect resources
US6202119B1 (en) 1997-12-19 2001-03-13 Micron Technology, Inc. Method and system for processing pipelined memory commands
JP4226686B2 (ja) 1998-05-07 2009-02-18 株式会社東芝 半導体メモリシステム及び半導体メモリのアクセス制御方法及び半導体メモリ
US6750910B1 (en) * 1998-07-15 2004-06-15 Texas Instruments Incorporated Optical black and offset correction in CCD signal processing
US6175905B1 (en) 1998-07-30 2001-01-16 Micron Technology, Inc. Method and system for bypassing pipelines in a pipelined memory command generator
US6178488B1 (en) 1998-08-27 2001-01-23 Micron Technology, Inc. Method and apparatus for processing pipelined memory commands
US6996213B1 (en) * 1998-09-29 2006-02-07 Sun Microsystems, Inc. Superposition of data over voice
US6748442B1 (en) * 1998-12-21 2004-06-08 Advanced Micro Devices, Inc. Method and apparatus for using a control signal on a packet based communication link
WO2000077640A1 (en) 1999-06-10 2000-12-21 Belle Gate Investment B.V. Arrangements storing different versions of a set of data in separate memory areas and method for updating a set of data in a memory
US6708248B1 (en) 1999-07-23 2004-03-16 Rambus Inc. Memory system with channel multiplexing of multiple memory devices
WO2001040910A1 (en) * 1999-12-06 2001-06-07 De Jong, Eduard, Karel Computer arrangement using non-refreshed dram
BR9917573A (pt) * 1999-12-07 2002-08-06 Sun Microsystems Inc Dispositiivo de identiificação que contém uma foto segura, assim como um meio e método para autenticação de tal dispositiivo de identificação
ATE378679T1 (de) 1999-12-07 2007-11-15 Sun Microsystems Inc Computerlesbares medium mit mikroprozessor zur lesesteuerung und computeranordnung zur kommunikation mit einem derartigen medium
WO2001042929A1 (en) * 1999-12-08 2001-06-14 Rambus Inc Memory system with channel multiplexing of multiple memory devices
US7012613B1 (en) 2000-05-02 2006-03-14 Ati International Srl Method and apparatus for fragment scriptor for use in over-sampling anti-aliasing
EP1307884A2 (de) * 2000-07-07 2003-05-07 Mosaid Technologies Incorporated Hochgeschwindigkeitsarchitektur einer dynamischen halbleiterspeicheranordnung mit wahlfreiem zugriff (dram) mit gleichförmiger zugriffslatenzzeit
CA2416844A1 (en) 2000-07-20 2002-01-31 Belle Gate Investment B.V. Method and system of communicating devices, and devices therefor, with protected data transfer
US6900812B1 (en) * 2000-08-02 2005-05-31 Ati International Srl Logic enhanced memory and method therefore
KR100401490B1 (ko) * 2000-10-31 2003-10-11 주식회사 하이닉스반도체 로오 버퍼를 내장한 반도체 메모리 장치
DE10059553B4 (de) * 2000-11-30 2005-04-28 Infineon Technologies Ag Schaltungsanordnung und Verfahren zum Synchronisieren
US6557090B2 (en) * 2001-03-09 2003-04-29 Micron Technology, Inc. Column address path circuit and method for memory devices having a burst access mode
US6622203B2 (en) * 2001-05-29 2003-09-16 Agilent Technologies, Inc. Embedded memory access method and system for application specific integrated circuits
DE10164338A1 (de) * 2001-12-28 2003-07-17 Thomson Brandt Gmbh Verfahren zur Einstellung eines Betriebsparameters in einem Peripherie-IC und Vorrichtung zur Durchführung des Verfahrens
US6829184B2 (en) * 2002-01-28 2004-12-07 Intel Corporation Apparatus and method for encoding auto-precharge
US6721227B2 (en) * 2002-02-11 2004-04-13 Micron Technology, Inc. User selectable banks for DRAM
US20030163654A1 (en) * 2002-02-22 2003-08-28 Eliel Louzoun System and method for efficient scheduling of memory
KR100452328B1 (ko) * 2002-07-31 2004-10-12 삼성전자주식회사 동기식 반도체 메모리 장치의 데이터 출력회로
KR100505109B1 (ko) * 2003-03-26 2005-07-29 삼성전자주식회사 읽기 시간을 단축시킬 수 있는 플래시 메모리 장치
US7496753B2 (en) * 2004-09-02 2009-02-24 International Business Machines Corporation Data encryption interface for reducing encrypt latency impact on standard traffic
US7409558B2 (en) * 2004-09-02 2008-08-05 International Business Machines Corporation Low-latency data decryption interface
KR100649834B1 (ko) * 2004-10-22 2006-11-28 주식회사 하이닉스반도체 반도체 메모리 소자의 누설 전류 제어 장치
DE102006053072B4 (de) * 2006-11-10 2014-09-04 Qimonda Ag Verfahren zum Auslesen von Datenpaketen
KR100856069B1 (ko) * 2007-03-29 2008-09-02 주식회사 하이닉스반도체 반도체 메모리 장치 및 그의 구동방법
US8006032B2 (en) * 2007-08-22 2011-08-23 Globalfoundries Inc. Optimal solution to control data channels
US7787311B2 (en) * 2007-11-08 2010-08-31 Rao G R Mohan Memory with programmable address strides for accessing and precharging during the same access cycle
US9978437B2 (en) 2015-12-11 2018-05-22 Micron Technology, Inc. Apparatuses and methods for dynamic voltage and frequency switching for dynamic random access memory
WO2017191706A1 (ja) * 2016-05-02 2017-11-09 ソニー株式会社 メモリ制御回路、メモリ、記憶装置、および、情報処理システム
KR102576767B1 (ko) 2018-12-03 2023-09-12 에스케이하이닉스 주식회사 반도체장치
CN110941395B (zh) * 2019-11-15 2023-06-16 深圳宏芯宇电子股份有限公司 动态随机存取存储器、内存管理方法、系统及存储介质

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58115674A (ja) * 1981-12-28 1983-07-09 Nec Corp 記憶装置
JPS6015771A (ja) * 1983-07-08 1985-01-26 Hitachi Ltd ベクトルプロセッサ
US4633434A (en) * 1984-04-02 1986-12-30 Sperry Corporation High performance storage unit
US4954946A (en) * 1986-01-29 1990-09-04 Digital Equipment Corporation Apparatus and method for providing distribution control in a main memory unit of a data processing system
EP0315671A1 (de) * 1987-06-02 1989-05-17 Hughes Aircraft Company Pipelinespeicherstruktur
US4845677A (en) * 1987-08-17 1989-07-04 International Business Machines Corporation Pipelined memory chip structure having improved cycle time
US5043883A (en) * 1987-12-17 1991-08-27 Hitachi, Ltd. Pipe-lined data processor system of synchronous type having memory devices with buffer memory and input/output data control
US5172379A (en) * 1989-02-24 1992-12-15 Data General Corporation High performance memory system
JPH02310887A (ja) * 1989-05-25 1990-12-26 Nec Corp パイプラインメモリ
US5060145A (en) * 1989-09-06 1991-10-22 Unisys Corporation Memory access system for pipelined data paths to and from storage
JP3179788B2 (ja) * 1991-01-17 2001-06-25 三菱電機株式会社 半導体記憶装置
US5247644A (en) * 1991-02-06 1993-09-21 Advanced Micro Devices, Inc. Processing system with improved sequential memory accessing
JP2625277B2 (ja) * 1991-05-20 1997-07-02 富士通株式会社 メモリアクセス装置
US5384745A (en) * 1992-04-27 1995-01-24 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device
JP3280704B2 (ja) * 1992-05-29 2002-05-13 株式会社東芝 半導体記憶装置
JP3078934B2 (ja) * 1992-12-28 2000-08-21 富士通株式会社 同期型ランダムアクセスメモリ
US5537555A (en) * 1993-03-22 1996-07-16 Compaq Computer Corporation Fully pipelined and highly concurrent memory controller
US5410670A (en) * 1993-06-02 1995-04-25 Microunity Systems Engineering, Inc. Accessing system that reduces access times due to transmission delays and I/O access circuitry in a burst mode random access memory
GR940100383A (en) * 1994-08-02 1996-04-30 Idryma Technologias & Erevnas A high-throughput data buffer.
US5737748A (en) * 1995-03-15 1998-04-07 Texas Instruments Incorporated Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory
US5745118A (en) * 1995-06-06 1998-04-28 Hewlett-Packard Company 3D bypass for download of textures
US5598374A (en) * 1995-07-14 1997-01-28 Cirrus Logic, Inc. Pipeland address memories, and systems and methods using the same
US5748914A (en) * 1995-10-19 1998-05-05 Rambus, Inc. Protocol for communication with dynamic memory
US5784705A (en) * 1996-07-15 1998-07-21 Mosys, Incorporated Method and structure for performing pipeline burst accesses in a semiconductor memory

Also Published As

Publication number Publication date
EP0788110B1 (de) 2003-10-22
JPH09213068A (ja) 1997-08-15
US6163832A (en) 2000-12-19
US6507900B1 (en) 2003-01-14
US6055615A (en) 2000-04-25
EP0788110A3 (de) 1999-02-03
KR970063250A (ko) 1997-09-12
KR100267962B1 (ko) 2000-10-16
EP0788110A2 (de) 1997-08-06
DE69725632T2 (de) 2004-06-17
TW332294B (en) 1998-05-21
JP4084428B2 (ja) 2008-04-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE