DE69727465D1 - Rechnersystem mit Speichersteuerung für Stossbetrieb-Übertragung - Google Patents

Rechnersystem mit Speichersteuerung für Stossbetrieb-Übertragung

Info

Publication number
DE69727465D1
DE69727465D1 DE69727465T DE69727465T DE69727465D1 DE 69727465 D1 DE69727465 D1 DE 69727465D1 DE 69727465 T DE69727465 T DE 69727465T DE 69727465 T DE69727465 T DE 69727465T DE 69727465 D1 DE69727465 D1 DE 69727465D1
Authority
DE
Germany
Prior art keywords
computer system
memory control
burst mode
mode transmission
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69727465T
Other languages
English (en)
Other versions
DE69727465T2 (de
Inventor
Dominic Paul Mccarthy
Victor Stuart Quick
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP97300113A external-priority patent/EP0853283A1/de
Priority claimed from GBGB9723704.4A external-priority patent/GB9723704D0/en
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE69727465D1 publication Critical patent/DE69727465D1/de
Application granted granted Critical
Publication of DE69727465T2 publication Critical patent/DE69727465T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/28—DMA
    • G06F2213/2806—Space or buffer allocation for DMA transfers
DE69727465T 1997-01-09 1997-11-26 Rechnersystem mit Speichersteuerung für Stossbetrieb-Übertragung Expired - Lifetime DE69727465T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP97300113A EP0853283A1 (de) 1997-01-09 1997-01-09 Rechnersystem mit Speichersteuerung für Stossbetrieb-Übertragung
EP97300113 1997-01-09
GB9723704 1997-11-11
GBGB9723704.4A GB9723704D0 (en) 1997-11-11 1997-11-11 Computer systems

Publications (2)

Publication Number Publication Date
DE69727465D1 true DE69727465D1 (de) 2004-03-11
DE69727465T2 DE69727465T2 (de) 2004-12-23

Family

ID=26147251

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69727465T Expired - Lifetime DE69727465T2 (de) 1997-01-09 1997-11-26 Rechnersystem mit Speichersteuerung für Stossbetrieb-Übertragung

Country Status (3)

Country Link
US (2) US6321310B1 (de)
JP (1) JP4142141B2 (de)
DE (1) DE69727465T2 (de)

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US8572302B1 (en) * 2006-10-13 2013-10-29 Marvell International Ltd. Controller for storage device with improved burst efficiency
US7617354B2 (en) * 2007-03-08 2009-11-10 Qimonda North America Corp. Abbreviated burst data transfers for semiconductor memory
KR100891508B1 (ko) * 2007-03-16 2009-04-06 삼성전자주식회사 가상 디엠에이를 포함하는 시스템
US8806461B2 (en) * 2007-06-21 2014-08-12 Microsoft Corporation Using memory usage to pinpoint sub-optimal code for gaming systems
US7730244B1 (en) * 2008-03-27 2010-06-01 Xilinx, Inc. Translation of commands in an interconnection of an embedded processor block core in an integrated circuit
US8386664B2 (en) * 2008-05-22 2013-02-26 International Business Machines Corporation Reducing runtime coherency checking with global data flow analysis
US8281295B2 (en) * 2008-05-23 2012-10-02 International Business Machines Corporation Computer analysis and runtime coherency checking
US8285670B2 (en) 2008-07-22 2012-10-09 International Business Machines Corporation Dynamically maintaining coherency within live ranges of direct buffers
JP2010146084A (ja) * 2008-12-16 2010-07-01 Toshiba Corp キャッシュメモリ制御部を備えるデータ処理装置
US9417685B2 (en) * 2013-01-07 2016-08-16 Micron Technology, Inc. Power management
KR102449333B1 (ko) * 2015-10-30 2022-10-04 삼성전자주식회사 메모리 시스템 및 그것의 읽기 요청 관리 방법
US9965326B1 (en) * 2016-06-27 2018-05-08 Rockwell Collins, Inc. Prediction and management of multi-core computation deration
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EP0853283A1 (de) 1997-01-09 1998-07-15 Hewlett-Packard Company Rechnersystem mit Speichersteuerung für Stossbetrieb-Übertragung

Also Published As

Publication number Publication date
JP4142141B2 (ja) 2008-08-27
US6336154B1 (en) 2002-01-01
US6321310B1 (en) 2001-11-20
JPH10232826A (ja) 1998-09-02
DE69727465T2 (de) 2004-12-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE