DE69802209T2 - An bytebereiche innerhalb eines befehlscaches gebundene verzweigungsselektoren zur schnellen identifizierung von verzweigungsprädiktoren - Google Patents

An bytebereiche innerhalb eines befehlscaches gebundene verzweigungsselektoren zur schnellen identifizierung von verzweigungsprädiktoren

Info

Publication number
DE69802209T2
DE69802209T2 DE69802209T DE69802209T DE69802209T2 DE 69802209 T2 DE69802209 T2 DE 69802209T2 DE 69802209 T DE69802209 T DE 69802209T DE 69802209 T DE69802209 T DE 69802209T DE 69802209 T2 DE69802209 T2 DE 69802209T2
Authority
DE
Germany
Prior art keywords
branch
tied
sectors
quick identification
command cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69802209T
Other languages
English (en)
Other versions
DE69802209D1 (de
Inventor
M Tran
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69802209D1 publication Critical patent/DE69802209D1/de
Publication of DE69802209T2 publication Critical patent/DE69802209T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
DE69802209T 1997-10-24 1998-06-13 An bytebereiche innerhalb eines befehlscaches gebundene verzweigungsselektoren zur schnellen identifizierung von verzweigungsprädiktoren Expired - Lifetime DE69802209T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/957,596 US5978906A (en) 1996-11-19 1997-10-24 Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions
PCT/US1998/012383 WO1999022293A1 (en) 1997-10-24 1998-06-13 Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions

Publications (2)

Publication Number Publication Date
DE69802209D1 DE69802209D1 (de) 2001-11-29
DE69802209T2 true DE69802209T2 (de) 2002-06-27

Family

ID=25499819

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69802209T Expired - Lifetime DE69802209T2 (de) 1997-10-24 1998-06-13 An bytebereiche innerhalb eines befehlscaches gebundene verzweigungsselektoren zur schnellen identifizierung von verzweigungsprädiktoren

Country Status (6)

Country Link
US (3) US5978906A (de)
EP (1) EP1025488B1 (de)
JP (1) JP3794917B2 (de)
KR (1) KR100577445B1 (de)
DE (1) DE69802209T2 (de)
WO (1) WO1999022293A1 (de)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5978906A (en) * 1996-11-19 1999-11-02 Advanced Micro Devices, Inc. Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions
US6253316B1 (en) 1996-11-19 2001-06-26 Advanced Micro Devices, Inc. Three state branch history using one bit in a branch prediction mechanism
US5995749A (en) 1996-11-19 1999-11-30 Advanced Micro Devices, Inc. Branch prediction mechanism employing branch selectors to select a branch prediction
US6253309B1 (en) 1998-09-21 2001-06-26 Advanced Micro Devices, Inc. Forcing regularity into a CISC instruction set by padding instructions
US6460116B1 (en) 1998-09-21 2002-10-01 Advanced Micro Devices, Inc. Using separate caches for variable and generated fixed-length instructions
US6275927B2 (en) 1998-09-21 2001-08-14 Advanced Micro Devices. Compressing variable-length instruction prefix bytes
US6339822B1 (en) * 1998-10-02 2002-01-15 Advanced Micro Devices, Inc. Using padded instructions in a block-oriented cache
US6240506B1 (en) 1998-10-02 2001-05-29 Advanced Micro Devices, Inc. Expanding instructions with variable-length operands to a fixed length
JP3522135B2 (ja) * 1998-12-10 2004-04-26 富士通株式会社 複数のウェイを持つブランチヒストリを備える情報処理装置
KR100347865B1 (ko) * 1999-11-15 2002-08-09 삼성전자 주식회사 어드레스 트레이스를 이용한 분기 예측 방법
US6502188B1 (en) 1999-11-16 2002-12-31 Advanced Micro Devices, Inc. Dynamic classification of conditional branches in global history branch prediction
US6581138B2 (en) * 2000-02-29 2003-06-17 Stmicroelectronics, Inc. Branch-prediction driven instruction prefetch
US6735689B1 (en) * 2000-05-01 2004-05-11 Raza Microelectronics, Inc. Method and system for reducing taken branch penalty
US7024545B1 (en) * 2001-07-24 2006-04-04 Advanced Micro Devices, Inc. Hybrid branch prediction device with two levels of branch prediction cache
US7302556B2 (en) * 2003-09-25 2007-11-27 International Business Machines Corporation Method, apparatus and computer program product for implementing level bias function for branch prediction control for generating test simulation vectors
US7752426B2 (en) * 2004-08-30 2010-07-06 Texas Instruments Incorporated Processes, circuits, devices, and systems for branch prediction and other processor improvements
US7890735B2 (en) * 2004-08-30 2011-02-15 Texas Instruments Incorporated Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture
US7328332B2 (en) * 2004-08-30 2008-02-05 Texas Instruments Incorporated Branch prediction and other processor improvements using FIFO for bypassing certain processor pipeline stages
KR100645108B1 (ko) * 2004-10-11 2006-11-10 김미옥 추락방지망 설치구조
KR100688503B1 (ko) * 2004-11-02 2007-03-02 삼성전자주식회사 브랜치 목적 어드레스를 이용하여 캐쉬 웨이를 예측하는프로세서 및 그 방법
US7280941B2 (en) * 2004-12-29 2007-10-09 General Electric Company Method and apparatus for in-situ detection and isolation of aircraft engine faults
EP2477109B1 (de) 2006-04-12 2016-07-13 Soft Machines, Inc. Vorrichtung und Verfahren zur Verarbeitung einer Anweisungsmatrix zur Spezifizierung von parallelen und abhängigen Betriebsabläufen
EP2523101B1 (de) 2006-11-14 2014-06-04 Soft Machines, Inc. Vorrichtung und Verfahren zum Verarbeiten von komplexen Anweisungsformaten in einer Multi-Thread-Architektur, die verschiedene Kontextschaltungsmodi und Visualisierungsschemen unterstützt
JP4980751B2 (ja) 2007-03-02 2012-07-18 富士通セミコンダクター株式会社 データ処理装置、およびメモリのリードアクティブ制御方法。
JP5145809B2 (ja) * 2007-07-31 2013-02-20 日本電気株式会社 分岐予測装置、ハイブリッド分岐予測装置、プロセッサ、分岐予測方法、及び分岐予測制御プログラム
US8782384B2 (en) * 2007-12-20 2014-07-15 Advanced Micro Devices, Inc. Branch history with polymorphic indirect branch information
US20110093658A1 (en) * 2009-10-19 2011-04-21 Zuraski Jr Gerald D Classifying and segregating branch targets
EP2616928B1 (de) * 2010-09-17 2016-11-02 Soft Machines, Inc. Mehrfach verzweigte einzelzyklus-vorhersage mit einem latenten cache für frühe und entfernte verzweigungsvorhersage
EP2689326B1 (de) 2011-03-25 2022-11-16 Intel Corporation Speicherfragmente zur unterstützung einer codeblockausführung mittels durch partitionierbare engines realisierter virtueller kerne
WO2012135031A2 (en) 2011-03-25 2012-10-04 Soft Machines, Inc. Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
WO2012162189A1 (en) 2011-05-20 2012-11-29 Soft Machines, Inc. An interconnect structure to support the execution of instruction sequences by a plurality of engines
CN103649932B (zh) 2011-05-20 2017-09-26 英特尔公司 资源的分散分配以及用于支持由多个引擎执行指令序列的互连结构
KR101703401B1 (ko) 2011-11-22 2017-02-06 소프트 머신즈, 인크. 다중 엔진 마이크로프로세서용 가속 코드 최적화기
US20150039859A1 (en) 2011-11-22 2015-02-05 Soft Machines, Inc. Microprocessor accelerated code optimizer
US9395994B2 (en) 2011-12-30 2016-07-19 Intel Corporation Embedded branch prediction unit
US9396117B2 (en) 2012-01-09 2016-07-19 Nvidia Corporation Instruction cache power reduction
US9547358B2 (en) * 2012-04-27 2017-01-17 Nvidia Corporation Branch prediction power reduction
US9552032B2 (en) * 2012-04-27 2017-01-24 Nvidia Corporation Branch prediction power reduction
US9201658B2 (en) 2012-09-24 2015-12-01 Apple Inc. Branch predictor for wide issue, arbitrarily aligned fetch that can cross cache line boundaries
KR102083390B1 (ko) 2013-03-15 2020-03-02 인텔 코포레이션 네이티브 분산된 플래그 아키텍처를 이용하여 게스트 중앙 플래그 아키텍처를 에뮬레이션하는 방법
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
KR102063656B1 (ko) 2013-03-15 2020-01-09 소프트 머신즈, 인크. 블록들로 그룹화된 멀티스레드 명령어들을 실행하기 위한 방법
US11086629B2 (en) * 2018-11-09 2021-08-10 Arm Limited Misprediction of predicted taken branches in a data processing apparatus

Family Cites Families (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT354159B (de) * 1975-02-10 1979-12-27 Siemens Ag Assoziativspeicher mit getrennt assoziierbaren bereichen
US4179737A (en) * 1977-12-23 1979-12-18 Burroughs Corporation Means and methods for providing greater speed and flexibility of microinstruction sequencing
US4453212A (en) * 1981-07-13 1984-06-05 Burroughs Corporation Extended address generating apparatus and method
US4928223A (en) * 1982-10-06 1990-05-22 Fairchild Semiconductor Corporation Floating point microprocessor with directable two level microinstructions
US4807115A (en) * 1983-10-07 1989-02-21 Cornell Research Foundation, Inc. Instruction issuing mechanism for processors with multiple functional units
US4679141A (en) * 1985-04-29 1987-07-07 International Business Machines Corporation Pageable branch history table
DE3751503T2 (de) * 1986-03-26 1996-05-09 Hitachi Ltd Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen.
EP0259095A3 (de) * 1986-08-27 1990-02-28 Amdahl Corporation Warteschlange für einen Cachespeicher
US4860197A (en) * 1987-07-31 1989-08-22 Prime Computer, Inc. Branch cache system with instruction boundary determination independent of parcel boundary
US5067069A (en) * 1989-02-03 1991-11-19 Digital Equipment Corporation Control of multiple functional units with parallel operation in a microcoded execution unit
US5142634A (en) * 1989-02-03 1992-08-25 Digital Equipment Corporation Branch prediction
US5226126A (en) * 1989-02-24 1993-07-06 Nexgen Microsystems Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
JPH02287626A (ja) * 1989-04-28 1990-11-27 Toshiba Corp パイプライン方式の分岐命令制御装置
US5129067A (en) * 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements
US5136697A (en) * 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
WO1991004536A1 (en) * 1989-09-20 1991-04-04 Dolphin Server Technology A/S Instruction cache architecture for parallel issuing of multiple instructions
US5226130A (en) * 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
US5058048A (en) * 1990-04-02 1991-10-15 Advanced Micro Devices, Inc. Normalizing pipelined floating point processing unit
US5053631A (en) * 1990-04-02 1991-10-01 Advanced Micro Devices, Inc. Pipelined floating point processing unit
EP0459232B1 (de) * 1990-05-29 1998-12-09 National Semiconductor Corporation Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür
US5235697A (en) * 1990-06-29 1993-08-10 Digital Equipment Set prediction cache memory system using bits of the main memory address
GB2263985B (en) * 1992-02-06 1995-06-14 Intel Corp Two stage window multiplexors for deriving variable length instructions from a stream of instructions
GB2263987B (en) * 1992-02-06 1996-03-06 Intel Corp End bit markers for instruction decode
WO1993017385A1 (en) * 1992-02-27 1993-09-02 Intel Corporation Dynamic flow instruction cache memory
US5418922A (en) * 1992-04-30 1995-05-23 International Business Machines Corporation History table for set prediction for accessing a set associative cache
EP0586057B1 (de) * 1992-08-31 2000-03-01 Sun Microsystems, Inc. Schnelles Vorausholen und Zuteilung von Befehlen mittels vorausschauender Anmerkungen von früher vorausgeholten
US5367703A (en) * 1993-01-08 1994-11-22 International Business Machines Corporation Method and system for enhanced branch history prediction accuracy in a superscalar processor system
JP2744882B2 (ja) * 1993-01-15 1998-04-28 インターナショナル・ビジネス・マシーンズ・コーポレイション キューにより命令の実行を制御する装置及び方法
US5454117A (en) * 1993-08-25 1995-09-26 Nexgen, Inc. Configurable branch prediction for a processor performing speculative execution
IE80854B1 (en) * 1993-08-26 1999-04-07 Intel Corp Processor ordering consistency for a processor performing out-of-order instruction execution
JP3639927B2 (ja) * 1993-10-04 2005-04-20 株式会社ルネサステクノロジ データ処理装置
US5574871A (en) * 1994-01-04 1996-11-12 Intel Corporation Method and apparatus for implementing a set-associative branch target buffer
US5592634A (en) * 1994-05-16 1997-01-07 Motorola Inc. Zero-cycle multi-state branch cache prediction data processing system and method thereof
US5758142A (en) * 1994-05-31 1998-05-26 Digital Equipment Corporation Trainable apparatus for predicting instruction outcomes in pipelined processors
US5692168A (en) * 1994-10-18 1997-11-25 Cyrix Corporation Prefetch buffer using flow control bit to identify changes of flow within the code stream
US5732253A (en) * 1994-10-18 1998-03-24 Cyrix Corporation Branch processing unit with target cache storing history for predicted taken branches and history cache storing history for predicted not-taken branches
US5649137A (en) * 1994-10-20 1997-07-15 Advanced Micro Devices, Inc. Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
JP3494736B2 (ja) * 1995-02-27 2004-02-09 株式会社ルネサステクノロジ 分岐先バッファを用いた分岐予測システム
US5822574A (en) * 1995-04-12 1998-10-13 Advanced Micro Devices, Inc. Functional unit with a pointer for mispredicted resolution, and a superscalar microprocessor employing the same
US5764946A (en) * 1995-04-12 1998-06-09 Advanced Micro Devices Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address
US5875324A (en) 1995-06-07 1999-02-23 Advanced Micro Devices, Inc. Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock
US5968169A (en) 1995-06-07 1999-10-19 Advanced Micro Devices, Inc. Superscalar microprocessor stack structure for judging validity of predicted subroutine return addresses
US5878255A (en) 1995-06-07 1999-03-02 Advanced Micro Devices, Inc. Update unit for providing a delayed update to a branch prediction array
US5649178A (en) * 1995-06-07 1997-07-15 International Business Machines, Corporation Apparatus and method for storing and initializing branch prediction with selective information transfer
US5881278A (en) * 1995-10-30 1999-03-09 Advanced Micro Devices, Inc. Return address prediction system which adjusts the contents of return stack storage to enable continued prediction after a mispredicted branch
US5864707A (en) * 1995-12-11 1999-01-26 Advanced Micro Devices, Inc. Superscalar microprocessor configured to predict return addresses from a return stack storage
US5798906A (en) 1996-07-17 1998-08-25 Honda Giken Kogyo Kabushiki Kaisha Capacitor
US5822575A (en) * 1996-09-12 1998-10-13 Advanced Micro Devices, Inc. Branch prediction storage for storing branch prediction information such that a corresponding tag may be routed with the branch instruction
US5794028A (en) * 1996-10-17 1998-08-11 Advanced Micro Devices, Inc. Shared branch prediction structure
US5954816A (en) * 1996-11-19 1999-09-21 Advanced Micro Devices, Inc. Branch selector prediction
US5978906A (en) * 1996-11-19 1999-11-02 Advanced Micro Devices, Inc. Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions
US5995749A (en) * 1996-11-19 1999-11-30 Advanced Micro Devices, Inc. Branch prediction mechanism employing branch selectors to select a branch prediction

Also Published As

Publication number Publication date
JP2001521241A (ja) 2001-11-06
US5978906A (en) 1999-11-02
DE69802209D1 (de) 2001-11-29
KR100577445B1 (ko) 2006-05-09
EP1025488B1 (de) 2001-10-24
EP1025488A1 (de) 2000-08-09
KR20010031396A (ko) 2001-04-16
JP3794917B2 (ja) 2006-07-12
US6279107B1 (en) 2001-08-21
US6141748A (en) 2000-10-31
WO1999022293A1 (en) 1999-05-06

Similar Documents

Publication Publication Date Title
DE69802209D1 (de) An bytebereiche innerhalb eines befehlscaches gebundene verzweigungsselektoren zur schnellen identifizierung von verzweigungsprädiktoren
DE69534148D1 (de) Rechnersystem zur Ausführung von Verzweigungsbefehlen
DE69734093D1 (de) System zur Ausführung von Gleitkommaoperationen
DE69721643D1 (de) Multiprozessorsystem ausgestaltet zur effizienten Ausführung von Schreiboperationen
DE69713960D1 (de) Anzeige zur spontanen Benutzung eines Rechners
DE69728779D1 (de) Entfernung von fältchen
DE69739096D1 (de) System zur Vorbereitung von Biegedaten zur Durchführung eines Biegevorgangs
DE69615445D1 (de) Kompilierer zur Verbesserung der Leistung von Datencachespeichern
DE69739745D1 (de) Verfahren zum drahtlosen Auffinden von Informationen
DE69739384D1 (de) Multiprozessorsystem ausgestaltet zur Ausführung von softwareinitiierten Vorausladeoperationen
DE69408747T2 (de) Verfahren zur Prüfung von einer Rohrauskleidung
DE69421960T2 (de) Verfahren zur Reparatur von Rohrleitungen
DE59708038D1 (de) Verfahren zur Kennzeichnung von Programmkompatibilität
DE59703147D1 (de) Verwendung eines copolymerisats als lösungsmittelfestes textilbindemittel
FR2743490B1 (fr) Agrafe d'arthrodese et instruments ancillaires pour la pose d'une telle agrafe
ITTO950686A1 (it) Procedimento di spurgo di un sistema idraulico
DE59800958D1 (de) Radarsystem zum Abbilden von Sektoren
DE59505798D1 (de) Kühlsystem zur kühlung eines zur aufnahme von kernschmelze ausgelegten rückhalteraums
DE9300423U1 (de) Niederhaltevorrichtung für eine Bremsbacke einer Trommelbremse
DE59808726D1 (de) System zur Spracherkennung von Ziffern
DE59705708D1 (de) Lagebestimmung von peripherieeinheiten
DE69732989D1 (de) Prüfung von Identifikationssignalen
DE59208579D1 (de) Verfahren zur Erkennung eines Zieles
DE69707882T2 (de) Carbonylierungsverfahren der pentensäuren
DE69827907D1 (de) Verbesserung eines zweiteiligen Grenzsteines

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES, INC., GARAND CAYMAN, KY