DE69802663T2 - Hochgeschwindigkeitsprüfsystem für speichereinrichtung - Google Patents
Hochgeschwindigkeitsprüfsystem für speichereinrichtungInfo
- Publication number
- DE69802663T2 DE69802663T2 DE69802663T DE69802663T DE69802663T2 DE 69802663 T2 DE69802663 T2 DE 69802663T2 DE 69802663 T DE69802663 T DE 69802663T DE 69802663 T DE69802663 T DE 69802663T DE 69802663 T2 DE69802663 T2 DE 69802663T2
- Authority
- DE
- Germany
- Prior art keywords
- line
- memory device
- data
- read
- circuitry
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/34—Accessing multiple bits simultaneously
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/779,036 US5966388A (en) | 1997-01-06 | 1997-01-06 | High-speed test system for a memory device |
| PCT/US1998/000455 WO1998031019A1 (en) | 1997-01-06 | 1998-01-06 | High-speed test system for a memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69802663D1 DE69802663D1 (de) | 2002-01-10 |
| DE69802663T2 true DE69802663T2 (de) | 2002-05-23 |
Family
ID=25115119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69802663T Expired - Lifetime DE69802663T2 (de) | 1997-01-06 | 1998-01-06 | Hochgeschwindigkeitsprüfsystem für speichereinrichtung |
Country Status (8)
| Country | Link |
|---|---|
| US (3) | US5966388A (de) |
| EP (1) | EP0948793B1 (de) |
| JP (1) | JP2001508223A (de) |
| KR (1) | KR100487176B1 (de) |
| AT (1) | ATE209821T1 (de) |
| AU (1) | AU5912398A (de) |
| DE (1) | DE69802663T2 (de) |
| WO (1) | WO1998031019A1 (de) |
Families Citing this family (72)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5966388A (en) * | 1997-01-06 | 1999-10-12 | Micron Technology, Inc. | High-speed test system for a memory device |
| US6173425B1 (en) | 1998-04-15 | 2001-01-09 | Integrated Device Technology, Inc. | Methods of testing integrated circuits to include data traversal path identification information and related status information in test data streams |
| JPH11306798A (ja) * | 1998-04-22 | 1999-11-05 | Oki Electric Ind Co Ltd | メモリ装置のテスト容易化回路 |
| US6178532B1 (en) * | 1998-06-11 | 2001-01-23 | Micron Technology, Inc. | On-chip circuit and method for testing memory devices |
| JP3292145B2 (ja) * | 1998-06-26 | 2002-06-17 | 日本電気株式会社 | 半導体記憶装置 |
| US6115303A (en) * | 1998-10-09 | 2000-09-05 | Micron Technology, Inc. | Method and apparatus for testing memory devices |
| JP2000322899A (ja) * | 1999-05-12 | 2000-11-24 | Nec Corp | 半導体装置、そのテスト装置及びそのテスト方法 |
| KR100529394B1 (ko) * | 1999-06-28 | 2005-11-17 | 주식회사 하이닉스반도체 | 테스트 구현을 위한 반도체메모리장치의 데이터 압축 회로 |
| US6484289B1 (en) * | 1999-09-23 | 2002-11-19 | Texas Instruments Incorporated | Parallel data test for a semiconductor memory |
| JP3732702B2 (ja) * | 2000-01-31 | 2006-01-11 | 株式会社リコー | 画像処理装置 |
| JP3734408B2 (ja) * | 2000-07-03 | 2006-01-11 | シャープ株式会社 | 半導体記憶装置 |
| US7978219B1 (en) | 2000-08-30 | 2011-07-12 | Kevin Reid Imes | Device, network, server, and methods for providing digital images and associated processing information |
| US8326352B1 (en) | 2000-09-06 | 2012-12-04 | Kevin Reid Imes | Device, network, server, and methods for providing service requests for wireless communication devices |
| US6812726B1 (en) | 2002-11-27 | 2004-11-02 | Inapac Technology, Inc. | Entering test mode and accessing of a packaged semiconductor device |
| US7444575B2 (en) * | 2000-09-21 | 2008-10-28 | Inapac Technology, Inc. | Architecture and method for testing of an integrated circuit device |
| US6754866B1 (en) * | 2001-09-28 | 2004-06-22 | Inapac Technology, Inc. | Testing of integrated circuit devices |
| US7240254B2 (en) * | 2000-09-21 | 2007-07-03 | Inapac Technology, Inc | Multiple power levels for a chip within a multi-chip semiconductor package |
| US6732304B1 (en) * | 2000-09-21 | 2004-05-04 | Inapac Technology, Inc. | Chip testing within a multi-chip semiconductor package |
| ITRM20010104A1 (it) * | 2001-02-27 | 2002-08-27 | Micron Technology Inc | Modo di lettura a compressione di dati per il collaudo di memorie. |
| US6449203B1 (en) | 2001-03-08 | 2002-09-10 | Micron Technology, Inc. | Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs |
| DE10129625A1 (de) * | 2001-06-20 | 2003-01-02 | Infineon Technologies Ag | Vorrichtung und Verfahren zum Testen einer Einrichtung zum Speichern von Daten |
| US8286046B2 (en) | 2001-09-28 | 2012-10-09 | Rambus Inc. | Integrated circuit testing module including signal shaping interface |
| US8166361B2 (en) | 2001-09-28 | 2012-04-24 | Rambus Inc. | Integrated circuit testing module configured for set-up and hold time testing |
| US7265570B2 (en) * | 2001-09-28 | 2007-09-04 | Inapac Technology, Inc. | Integrated circuit testing module |
| US7313740B2 (en) * | 2002-07-25 | 2007-12-25 | Inapac Technology, Inc. | Internally generating patterns for testing in an integrated circuit device |
| US20040019841A1 (en) * | 2002-07-25 | 2004-01-29 | Ong Adrian E. | Internally generating patterns for testing in an integrated circuit device |
| US7370256B2 (en) * | 2001-09-28 | 2008-05-06 | Inapac Technology, Inc. | Integrated circuit testing module including data compression |
| US8001439B2 (en) | 2001-09-28 | 2011-08-16 | Rambus Inc. | Integrated circuit testing module including signal shaping interface |
| US7446551B1 (en) | 2001-09-28 | 2008-11-04 | Inapac Technology, Inc. | Integrated circuit testing module including address generator |
| US7365557B1 (en) | 2001-09-28 | 2008-04-29 | Inapac Technology, Inc. | Integrated circuit testing module including data generator |
| US7206369B2 (en) * | 2001-10-12 | 2007-04-17 | Agere Systems Inc. | Programmable feedback delay phase-locked loop for high-speed input/output timing budget management and method of operation thereof |
| US6751159B2 (en) * | 2001-10-26 | 2004-06-15 | Micron Technology, Inc. | Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode |
| US7061263B1 (en) | 2001-11-15 | 2006-06-13 | Inapac Technology, Inc. | Layout and use of bond pads and probe pads for testing of integrated circuits devices |
| US6754094B2 (en) * | 2002-01-31 | 2004-06-22 | Stmicroelectronics, Inc. | Circuit and method for testing a ferroelectric memory device |
| US20030182609A1 (en) * | 2002-01-31 | 2003-09-25 | Shirish Agrawal | Pass gate multiplexer |
| US6838331B2 (en) * | 2002-04-09 | 2005-01-04 | Micron Technology, Inc. | Method and system for dynamically operating memory in a power-saving error correction mode |
| US6751143B2 (en) * | 2002-04-11 | 2004-06-15 | Micron Technology, Inc. | Method and system for low power refresh of dynamic random access memories |
| JP4447200B2 (ja) * | 2002-07-19 | 2010-04-07 | Ｎｅｃエレクトロニクス株式会社 | 映像データ転送方法、表示制御回路及び液晶表示装置 |
| US7055076B2 (en) * | 2002-08-28 | 2006-05-30 | Micron Technology, Inc. | Output data compression scheme using tri-state |
| DE10245713B4 (de) * | 2002-10-01 | 2004-10-28 | Infineon Technologies Ag | Testsystem und Verfahren zum Testen von Speicherschaltungen |
| US8063650B2 (en) | 2002-11-27 | 2011-11-22 | Rambus Inc. | Testing fuse configurations in semiconductor devices |
| ITRM20030040A1 (it) * | 2003-01-31 | 2004-08-01 | Micron Technology Inc | Modo di lettura a compressione di dati per collaudo di memorie. |
| KR100527535B1 (ko) * | 2003-04-17 | 2005-11-09 | 주식회사 하이닉스반도체 | 입출력 압축 회로 |
| KR100541048B1 (ko) * | 2003-06-16 | 2006-01-11 | 삼성전자주식회사 | 반도체 메모리 장치 및 이 장치의 테스트 방법 |
| US6961269B2 (en) * | 2003-06-24 | 2005-11-01 | Micron Technology, Inc. | Memory device having data paths with multiple speeds |
| DE102004024668A1 (de) * | 2004-05-18 | 2005-12-15 | Infineon Technologies Ag | Verfahren zum Testen von elektronischen Schaltungseinheiten und Testvorrichtung |
| DE102004027275A1 (de) * | 2004-06-04 | 2005-12-29 | Infineon Technologies Ag | Integrierter Halbleiterspeicher |
| ITRM20040418A1 (it) * | 2004-08-25 | 2004-11-25 | Micron Technology Inc | Modo di lettura a compressione di dati a piu' livelli per il collaudo di memorie. |
| JP4370527B2 (ja) * | 2005-05-20 | 2009-11-25 | エルピーダメモリ株式会社 | 半導体記憶装置 |
| KR100648490B1 (ko) * | 2005-10-17 | 2006-11-27 | 삼성전자주식회사 | 반도체 메모리 장치의 테스트 회로, 테스트 방법, 및 이를포함하는 반도체 메모리 장치 |
| KR100668496B1 (ko) | 2005-11-09 | 2007-01-12 | 주식회사 하이닉스반도체 | 데이터 압축 회로 |
| US20070109888A1 (en) * | 2005-11-14 | 2007-05-17 | Ronald Baker | Integrated circuit with test circuit |
| US7457177B2 (en) | 2005-12-21 | 2008-11-25 | Infineon Technologies Ag | Random access memory including circuit to compress comparison results |
| KR100695437B1 (ko) * | 2006-04-13 | 2007-03-16 | 주식회사 하이닉스반도체 | 멀티 포트 메모리 소자 |
| US7292487B1 (en) | 2006-05-10 | 2007-11-06 | Micron Technology, Inc. | Independent polling for multi-page programming |
| DE102006024016B4 (de) * | 2006-05-23 | 2008-04-03 | Infineon Technologies Ag | Speicher mit einem Ausgangsregister für Testdaten und Verfahren zum Testen eines Speichers |
| KR100809070B1 (ko) * | 2006-06-08 | 2008-03-03 | 삼성전자주식회사 | 반도체 메모리 장치의 병렬 비트 테스트 회로 및 그 방법 |
| US7466603B2 (en) | 2006-10-03 | 2008-12-16 | Inapac Technology, Inc. | Memory accessing circuit system |
| US20080112255A1 (en) * | 2006-11-15 | 2008-05-15 | Aaron John Nygren | Training of signal transfer channels between memory controller and memory device |
| US20080291760A1 (en) * | 2007-05-23 | 2008-11-27 | Micron Technology, Inc. | Sub-array architecture memory devices and related systems and methods |
| US20090225610A1 (en) * | 2008-03-05 | 2009-09-10 | Wolfgang Hokenmaier | Integrated circuit that selectively outputs subsets of a group of data bits |
| US8489912B2 (en) * | 2009-09-09 | 2013-07-16 | Ati Technologies Ulc | Command protocol for adjustment of write timing delay |
| TWI451428B (zh) | 2010-06-03 | 2014-09-01 | Sunplus Technology Co Ltd | 於完整記憶體系統中具有先進特徵的記憶體測試系統 |
| KR101208960B1 (ko) * | 2010-11-26 | 2012-12-06 | 에스케이하이닉스 주식회사 | 반도체 장치 및 이의 테스트 방법 |
| US8713383B2 (en) * | 2010-12-30 | 2014-04-29 | Hynix Semiconductor Inc. | Semiconductor memory device, test circuit, and test operation method thereof |
| US8612812B2 (en) * | 2010-12-30 | 2013-12-17 | Hynix Semiconductor Inc. | Semiconductor memory device, test circuit, and test operation method thereof |
| US8595575B2 (en) * | 2010-12-30 | 2013-11-26 | Hynix Semiconductor Inc. | Semiconductor memory device, test circuit, and test operation method thereof |
| US8873305B2 (en) * | 2011-01-28 | 2014-10-28 | SK Hynix Inc. | Semiconductor memory device having data compression test circuit |
| KR20120113478A (ko) * | 2011-04-05 | 2012-10-15 | 삼성전자주식회사 | 반도체 메모리 장치의 테스트 방법 |
| US9412467B2 (en) * | 2014-04-29 | 2016-08-09 | Freescale Semiconductor, Inc. | Semiconductor device having a test controller and method of operation |
| KR102538991B1 (ko) * | 2016-07-15 | 2023-06-02 | 에스케이하이닉스 주식회사 | 반도체 테스트 장치 및 반도체 테스트 방법 |
| CN117059155A (zh) * | 2022-05-06 | 2023-11-14 | 长鑫存储技术有限公司 | 测试电路检查方法、测试平台、存储介质和测试系统 |
Family Cites Families (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4369511A (en) * | 1979-11-21 | 1983-01-18 | Nippon Telegraph & Telephone Public Corp. | Semiconductor memory test equipment |
| DE3751002T2 (de) * | 1986-10-20 | 1995-10-05 | Nippon Telegraph & Telephone | Halbleiterspeicher. |
| JP2613411B2 (ja) * | 1987-12-29 | 1997-05-28 | 株式会社アドバンテスト | メモリ試験装置 |
| KR910005306B1 (ko) * | 1988-12-31 | 1991-07-24 | 삼성전자 주식회사 | 고밀도 메모리의 테스트를 위한 병렬리드회로 |
| EP0389203A3 (de) * | 1989-03-20 | 1993-05-26 | Fujitsu Limited | Halbleiterspeichergerät beinhaltend Information, die die Anwesenheit mangelhafter Speicherzellen anzeigt |
| US5301155A (en) * | 1990-03-20 | 1994-04-05 | Mitsubishi Denki Kabushiki Kaisha | Multiblock semiconduction storage device including simultaneous operation of a plurality of block defect determination circuits |
| JPH0831279B2 (ja) * | 1990-12-20 | 1996-03-27 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 冗長システム |
| US5457696A (en) * | 1991-08-08 | 1995-10-10 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory having internal test circuit |
| KR100296850B1 (ko) * | 1992-05-28 | 2001-10-24 | 썬 마이크로시스템즈, 인코포레이티드 | 캐시램용다수의뱅크열용장성초기화제어기 |
| EP0578876A1 (de) * | 1992-06-30 | 1994-01-19 | Nec Corporation | Statische Speicher mit wahlfreiem Zugriff mit Speicherzellenprüfungsanordnung |
| JP3533227B2 (ja) * | 1992-09-10 | 2004-05-31 | 株式会社日立製作所 | 半導体記憶装置 |
| US5396124A (en) * | 1992-09-30 | 1995-03-07 | Matsushita Electric Industrial Co., Ltd. | Circuit redundancy having a variable impedance circuit |
| JP2741824B2 (ja) * | 1992-10-14 | 1998-04-22 | 三菱電機株式会社 | 半導体記憶装置 |
| JP2768175B2 (ja) * | 1992-10-26 | 1998-06-25 | 日本電気株式会社 | 半導体メモリ |
| JPH06242181A (ja) * | 1992-11-23 | 1994-09-02 | Texas Instr Inc <Ti> | 集積回路の試験装置及び方法 |
| KR960002016B1 (ko) * | 1993-02-15 | 1996-02-09 | 금성일렉트론주식회사 | 반도체 기억소자의 테스트 모드회로 |
| JP2616544B2 (ja) * | 1993-09-22 | 1997-06-04 | 日本電気株式会社 | 半導体記憶装置 |
| KR960008824B1 (en) * | 1993-11-17 | 1996-07-05 | Samsung Electronics Co Ltd | Multi bit test circuit and method of semiconductor memory device |
| JPH08161899A (ja) * | 1994-04-29 | 1996-06-21 | Texas Instr Inc <Ti> | メモリデバイスおよび半導体デバイステスト方法 |
| US5687387A (en) * | 1994-08-26 | 1997-11-11 | Packard Bell Nec | Enhanced active port replicator having expansion and upgrade capabilities |
| US5528539A (en) * | 1994-09-29 | 1996-06-18 | Micron Semiconductor, Inc. | High speed global row redundancy system |
| US5701441A (en) * | 1995-08-18 | 1997-12-23 | Xilinx, Inc. | Computer-implemented method of optimizing a design in a time multiplexed programmable logic device |
| US5925142A (en) * | 1995-10-06 | 1999-07-20 | Micron Technology, Inc. | Self-test RAM using external synchronous clock |
| JPH09128998A (ja) * | 1995-10-31 | 1997-05-16 | Nec Corp | テスト回路 |
| US5768287A (en) * | 1996-10-24 | 1998-06-16 | Micron Quantum Devices, Inc. | Apparatus and method for programming multistate memory device |
| US5966388A (en) * | 1997-01-06 | 1999-10-12 | Micron Technology, Inc. | High-speed test system for a memory device |
-
1997
- 1997-01-06 US US08/779,036 patent/US5966388A/en not_active Expired - Lifetime
-
1998
- 1998-01-06 AU AU59123/98A patent/AU5912398A/en not_active Abandoned
- 1998-01-06 WO PCT/US1998/000455 patent/WO1998031019A1/en active IP Right Grant
- 1998-01-06 DE DE69802663T patent/DE69802663T2/de not_active Expired - Lifetime
- 1998-01-06 AT AT98902471T patent/ATE209821T1/de not_active IP Right Cessation
- 1998-01-06 KR KR10-1999-7006129A patent/KR100487176B1/ko not_active IP Right Cessation
- 1998-01-06 EP EP98902471A patent/EP0948793B1/de not_active Expired - Lifetime
- 1998-01-06 JP JP53115298A patent/JP2001508223A/ja active Pending
-
1999
- 1999-05-27 US US09/321,295 patent/US6154860A/en not_active Expired - Lifetime
-
2000
- 2000-11-27 US US09/724,346 patent/US6550026B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| ATE209821T1 (de) | 2001-12-15 |
| US6154860A (en) | 2000-11-28 |
| EP0948793A1 (de) | 1999-10-13 |
| AU5912398A (en) | 1998-08-03 |
| US5966388A (en) | 1999-10-12 |
| KR20000069916A (ko) | 2000-11-25 |
| DE69802663D1 (de) | 2002-01-10 |
| JP2001508223A (ja) | 2001-06-19 |
| KR100487176B1 (ko) | 2005-05-03 |
| WO1998031019A1 (en) | 1998-07-16 |
| US6550026B1 (en) | 2003-04-15 |
| EP0948793B1 (de) | 2001-11-28 |
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