DE69810405D1 - Adiabatische Logikschaltung - Google Patents

Adiabatische Logikschaltung

Info

Publication number
DE69810405D1
DE69810405D1 DE69810405T DE69810405T DE69810405D1 DE 69810405 D1 DE69810405 D1 DE 69810405D1 DE 69810405 T DE69810405 T DE 69810405T DE 69810405 T DE69810405 T DE 69810405T DE 69810405 D1 DE69810405 D1 DE 69810405D1
Authority
DE
Germany
Prior art keywords
logic circuit
adiabatic logic
adiabatic
circuit
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69810405T
Other languages
English (en)
Other versions
DE69810405T2 (de
Inventor
Shunji Nakata
Takakuni Douseki
Mitsuru Harada
Ken Takeya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Publication of DE69810405D1 publication Critical patent/DE69810405D1/de
Application granted granted Critical
Publication of DE69810405T2 publication Critical patent/DE69810405T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0019—Arrangements for reducing power consumption by energy recovery or adiabatic operation
DE69810405T 1997-09-05 1998-09-04 Adiabatische Logikschaltung Expired - Fee Related DE69810405T2 (de)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP25622697 1997-09-05
JP3354698 1998-02-02
JP6032298 1998-02-26
JP8958298 1998-03-19
JP9694498 1998-03-26
JP16945998 1998-06-17

Publications (2)

Publication Number Publication Date
DE69810405D1 true DE69810405D1 (de) 2003-02-06
DE69810405T2 DE69810405T2 (de) 2003-11-27

Family

ID=27549692

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69810405T Expired - Fee Related DE69810405T2 (de) 1997-09-05 1998-09-04 Adiabatische Logikschaltung

Country Status (3)

Country Link
US (1) US6242951B1 (de)
EP (4) EP0901230B1 (de)
DE (1) DE69810405T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3821612B2 (ja) * 1999-07-09 2006-09-13 松下電器産業株式会社 不要輻射解析方法
JP3632151B2 (ja) 2000-06-06 2005-03-23 日本電信電話株式会社 断熱充電レジスタ回路
US6742132B2 (en) 2002-04-04 2004-05-25 The Regents Of The University Of Michigan Method and apparatus for generating a clock signal having a driven oscillator circuit formed with energy storage characteristics of a memory storage device
US7327168B2 (en) 2002-11-20 2008-02-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
CN100380811C (zh) * 2002-12-13 2008-04-09 株式会社半导体能源研究所 半导体器件和使用该半导体器件的显示器件
CN100338879C (zh) * 2002-12-25 2007-09-19 株式会社半导体能源研究所 配备了校正电路的数字电路及具有该数字电路的电子装置
US7973565B2 (en) * 2007-05-23 2011-07-05 Cyclos Semiconductor, Inc. Resonant clock and interconnect architecture for digital devices with multiple clock networks
WO2011046979A2 (en) * 2009-10-12 2011-04-21 Cyclos Semiconductor, Inc. Method for selecting natural frequency in resonant clock distribution networks with no inductor overhead
CN106921216B (zh) * 2015-12-28 2021-07-06 华邦电子股份有限公司 供应绝热电路操作的无线电力传输系统
US11023631B2 (en) * 2017-09-25 2021-06-01 Rezonent Corporation Reduced-power dynamic data circuits with wide-band energy recovery
US10340895B2 (en) 2017-09-25 2019-07-02 Rezonent Corporation Reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies
US10596807B2 (en) * 2018-03-19 2020-03-24 Fuji Xerox Co., Ltd. Capacitive load driving circuit and image forming apparatus
FR3088507B1 (fr) * 2018-11-09 2022-03-11 Commissariat Energie Atomique Cellule logique adiabatique

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5506519A (en) 1994-06-03 1996-04-09 At&T Corp. Low energy differential logic gate circuitry having substantially invariant clock signal loading
US5506520A (en) * 1995-01-11 1996-04-09 International Business Machines Corporation Energy conserving clock pulse generating circuits
US5493240A (en) 1995-03-01 1996-02-20 International Business Machines Corporation Static combinatorial logic circuits for reversible computation
US5521538A (en) 1995-03-30 1996-05-28 At&T Corp. Adiabatic logic
US5777491A (en) * 1995-03-31 1998-07-07 International Business Machines Corporation High-performance differential cascode voltage switch with pass gate logic elements
US5523707A (en) * 1995-06-30 1996-06-04 International Business Machines Corporation Fast, low power exclusive or circuit
US5602497A (en) * 1995-12-20 1997-02-11 Thomas; Steven D. Precharged adiabatic pipelined logic
JP3241619B2 (ja) * 1996-12-25 2001-12-25 シャープ株式会社 Ｃｍｏｓ論理回路
US5861762A (en) * 1997-03-07 1999-01-19 Sun Microsystems, Inc. Inverse toggle XOR and XNOR circuit

Also Published As

Publication number Publication date
US6242951B1 (en) 2001-06-05
EP1322040A1 (de) 2003-06-25
EP0901230A1 (de) 1999-03-10
DE69810405T2 (de) 2003-11-27
EP1326340A1 (de) 2003-07-09
EP1331738A1 (de) 2003-07-30
EP0901230B1 (de) 2003-01-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee