DE69826404D1 - Datenverarbeitungssystem mit mehreren Prozessoren, die eine Registerbank gemeinsam benutzen - Google Patents

Datenverarbeitungssystem mit mehreren Prozessoren, die eine Registerbank gemeinsam benutzen

Info

Publication number
DE69826404D1
DE69826404D1 DE69826404T DE69826404T DE69826404D1 DE 69826404 D1 DE69826404 D1 DE 69826404D1 DE 69826404 T DE69826404 T DE 69826404T DE 69826404 T DE69826404 T DE 69826404T DE 69826404 D1 DE69826404 D1 DE 69826404D1
Authority
DE
Germany
Prior art keywords
share
data processing
processing system
register bank
several processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69826404T
Other languages
English (en)
Other versions
DE69826404T2 (de
Inventor
Steven B Sidman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Sharp Microelectronics Technology Inc
Original Assignee
Sharp Corp
Sharp Microelectronics Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp, Sharp Microelectronics Technology Inc filed Critical Sharp Corp
Application granted granted Critical
Publication of DE69826404D1 publication Critical patent/DE69826404D1/de
Publication of DE69826404T2 publication Critical patent/DE69826404T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
DE69826404T 1997-10-20 1998-10-20 Datenverarbeitungssystem mit mehreren Prozessoren, die eine Registerbank gemeinsam benutzen Expired - Fee Related DE69826404T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US954541 1992-09-29
US08/954,541 US6029242A (en) 1995-08-16 1997-10-20 Data processing system using a shared register bank and a plurality of processors

Publications (2)

Publication Number Publication Date
DE69826404D1 true DE69826404D1 (de) 2004-10-28
DE69826404T2 DE69826404T2 (de) 2005-09-29

Family

ID=25495580

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69826404T Expired - Fee Related DE69826404T2 (de) 1997-10-20 1998-10-20 Datenverarbeitungssystem mit mehreren Prozessoren, die eine Registerbank gemeinsam benutzen

Country Status (5)

Country Link
US (1) US6029242A (de)
EP (1) EP0911725B1 (de)
JP (1) JPH11212786A (de)
DE (1) DE69826404T2 (de)
TW (1) TW499639B (de)

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* Cited by examiner, † Cited by third party
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JPH1165840A (ja) * 1997-08-11 1999-03-09 Sony Corp 演算処理装置およびその方法
US6212604B1 (en) 1998-12-03 2001-04-03 Sun Microsystems, Inc. Shared instruction cache for multiple processors
US7318090B1 (en) * 1999-10-20 2008-01-08 Sony Corporation Method for utilizing concurrent context switching to support isochronous processes
US6775752B1 (en) 2000-02-21 2004-08-10 Hewlett-Packard Development Company, L.P. System and method for efficiently updating a fully associative array
JP2002108837A (ja) * 2000-09-29 2002-04-12 Nec Corp 計算機システムとその計算制御方法
EP1346279A1 (de) * 2000-12-07 2003-09-24 Koninklijke Philips Electronics N.V. Digitale signalverarbeitungsvorrichtung
US7117346B2 (en) * 2002-05-31 2006-10-03 Freescale Semiconductor, Inc. Data processing system having multiple register contexts and method therefor
JP3784766B2 (ja) * 2002-11-01 2006-06-14 株式会社半導体理工学研究センター 多ポート統合キャッシュ
US20040098568A1 (en) * 2002-11-18 2004-05-20 Nguyen Hung T. Processor having a unified register file with multipurpose registers for storing address and data register values, and associated register mapping method
WO2005020077A1 (en) * 2003-08-13 2005-03-03 Thomson Licensing S.A. Dual bank shared data ram for efficient pipelined video and data processing
US8024551B2 (en) 2005-10-26 2011-09-20 Analog Devices, Inc. Pipelined digital signal processor
US8285972B2 (en) * 2005-10-26 2012-10-09 Analog Devices, Inc. Lookup table addressing system and method
US7600081B2 (en) * 2006-01-18 2009-10-06 Marvell World Trade Ltd. Processor architecture having multi-ported memory
US7882284B2 (en) * 2007-03-26 2011-02-01 Analog Devices, Inc. Compute unit with an internal bit FIFO circuit
US9020146B1 (en) * 2007-09-18 2015-04-28 Rockwell Collins, Inc. Algorithm agile programmable cryptographic processor
US8301990B2 (en) * 2007-09-27 2012-10-30 Analog Devices, Inc. Programmable compute unit with internal register and bit FIFO for executing Viterbi code
US8825926B2 (en) * 2009-04-13 2014-09-02 Microchip Technology Incorporated Processor with assignable general purpose register set
US9367462B2 (en) 2009-12-29 2016-06-14 Empire Technology Development Llc Shared memories for energy efficient multi-core processors
US8677150B2 (en) * 2012-02-01 2014-03-18 Intel Mobile Communications GmbH Low-power multi-standard cryptography processing units with common flip-flop/register banks
US20130275699A1 (en) * 2012-03-23 2013-10-17 Hicamp Systems, Inc. Special memory access path with segment-offset addressing
DE102014111305A1 (de) * 2014-08-07 2016-02-11 Mikro Pahlawan Prozessor-Modell, das ein einziges großes, lineares Register verwendet, mit FIFO-basierten I/O-Ports unterstützenden neuen Interface-Signalen und unterbrechungsgesteuerten Bus-Transfers, die DMA, Brücken und einen externen I/O-Bus eliminieren
GB2531058A (en) * 2014-10-10 2016-04-13 Aptcore Ltd Signal processing apparatus
EP3232321A1 (de) * 2016-04-12 2017-10-18 AptCore Ltd Signalverarbeitungsvorrichtung

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4630230A (en) * 1983-04-25 1986-12-16 Cray Research, Inc. Solid state storage device
US5142677A (en) * 1989-05-04 1992-08-25 Texas Instruments Incorporated Context switching devices, systems and methods
US5163132A (en) * 1987-09-24 1992-11-10 Ncr Corporation Integrated controller using alternately filled and emptied buffers for controlling bi-directional data transfer between a processor and a data storage device
EP0346031B1 (de) * 1988-06-07 1997-12-29 Fujitsu Limited Vektordatenverarbeitungsvorrichtung
US5222223A (en) * 1989-02-03 1993-06-22 Digital Equipment Corporation Method and apparatus for ordering and queueing multiple memory requests
US5185876A (en) * 1990-03-14 1993-02-09 Micro Technology, Inc. Buffering system for dynamically providing data to multiple storage elements
US5388217A (en) * 1991-12-13 1995-02-07 Cray Research, Inc. Distributing system for multi-processor input and output using channel adapters
US5418911A (en) * 1992-06-09 1995-05-23 Intel Corporation Data path switch method and apparatus that provides capacitive load isolation
US5507000A (en) * 1994-09-26 1996-04-09 Bull Hn Information Systems Inc. Sharing of register stack by two execution units in a central processor
US5680641A (en) * 1995-08-16 1997-10-21 Sharp Microelectronics Technology, Inc. Multiple register bank system for concurrent I/O operation in a CPU datapath
US5787304A (en) * 1996-02-05 1998-07-28 International Business Machines Corporation Multipath I/O storage systems with multipath I/O request mechanisms
US5913049A (en) * 1997-07-31 1999-06-15 Texas Instruments Incorporated Multi-stream complex instruction set microprocessor

Also Published As

Publication number Publication date
TW499639B (en) 2002-08-21
DE69826404T2 (de) 2005-09-29
JPH11212786A (ja) 1999-08-06
EP0911725A2 (de) 1999-04-28
US6029242A (en) 2000-02-22
EP0911725B1 (de) 2004-09-22
EP0911725A3 (de) 1999-11-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee