DE69829593D1 - Verfahren zur Prüfsequenzgenerierung - Google Patents

Verfahren zur Prüfsequenzgenerierung

Info

Publication number
DE69829593D1
DE69829593D1 DE69829593T DE69829593T DE69829593D1 DE 69829593 D1 DE69829593 D1 DE 69829593D1 DE 69829593 T DE69829593 T DE 69829593T DE 69829593 T DE69829593 T DE 69829593T DE 69829593 D1 DE69829593 D1 DE 69829593D1
Authority
DE
Germany
Prior art keywords
test sequence
sequence generation
generation
test
sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69829593T
Other languages
English (en)
Other versions
DE69829593T2 (de
Inventor
Toshinori Hosokawa
Mitsuyasu Ohta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69829593D1 publication Critical patent/DE69829593D1/de
Application granted granted Critical
Publication of DE69829593T2 publication Critical patent/DE69829593T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318392—Generation of test inputs, e.g. test vectors, patterns or sequences for sequential circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G01R31/318586—Design for test with partial scan or non-scannable parts
DE69829593T 1997-04-25 1998-04-24 Verfahren einer prüfsequenz-erzeugung Expired - Fee Related DE69829593T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10881397 1997-04-25
JP10881397 1997-04-25

Publications (2)

Publication Number Publication Date
DE69829593D1 true DE69829593D1 (de) 2005-05-04
DE69829593T2 DE69829593T2 (de) 2005-09-01

Family

ID=14494160

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69822694T Expired - Fee Related DE69822694T2 (de) 1997-04-25 1998-04-24 Verfahren zum prüfgerechten Entwurf, Verfahren zur Prüfsequenzerzeugung und integrierte Halbleiterschaltung
DE69829593T Expired - Fee Related DE69829593T2 (de) 1997-04-25 1998-04-24 Verfahren einer prüfsequenz-erzeugung

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69822694T Expired - Fee Related DE69822694T2 (de) 1997-04-25 1998-04-24 Verfahren zum prüfgerechten Entwurf, Verfahren zur Prüfsequenzerzeugung und integrierte Halbleiterschaltung

Country Status (4)

Country Link
US (2) US6253343B1 (de)
EP (2) EP1306684B1 (de)
DE (2) DE69822694T2 (de)
TW (1) TW413757B (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000067105A (ja) * 1998-06-08 2000-03-03 Matsushita Electric Ind Co Ltd 集積回路の検査容易化設計方法
US6865706B1 (en) * 2000-06-07 2005-03-08 Agilent Technologies, Inc. Apparatus and method for generating a set of test vectors using nonrandom filling
US7051253B2 (en) * 2001-08-16 2006-05-23 Infineon Technologies Richmond Lp Pseudo fail bit map generation for RAMS during component test and burn-in in a manufacturing environment
JP3785388B2 (ja) * 2002-09-17 2006-06-14 松下電器産業株式会社 故障検出方法
US7676453B2 (en) * 2004-04-22 2010-03-09 Oracle International Corporation Partial query caching
US7263675B2 (en) * 2004-06-03 2007-08-28 Synopsys, Inc. Tuple propagator and its use in analysis of mixed clock domain designs

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4779273A (en) * 1984-06-14 1988-10-18 Data General Corporation Apparatus for self-testing a digital logic circuit
JPS61122582A (ja) 1984-11-20 1986-06-10 Fujitsu Ltd 半導体集積回路装置
US4817093A (en) * 1987-06-18 1989-03-28 International Business Machines Corporation Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure
US5043986A (en) 1989-05-18 1991-08-27 At&T Bell Laboratories Method and integrated circuit adapted for partial scan testability
JP2616165B2 (ja) * 1989-07-12 1997-06-04 松下電器産業株式会社 検査入力生成方法および検査容易化設計方法
JP3265614B2 (ja) * 1991-04-16 2002-03-11 松下電器産業株式会社 検査系列生成方法
GB9121540D0 (en) 1991-10-10 1991-11-27 Smiths Industries Plc Computing systems and methods
US5377194A (en) 1991-12-16 1994-12-27 At&T Corp. Multiplexed coded modulation with unequal error protection
CZ383292A3 (en) 1992-02-18 1994-03-16 Koninkl Philips Electronics Nv Method of testing electronic circuits and an integrated circuit tested in such a manner
US5377197A (en) 1992-02-24 1994-12-27 University Of Illinois Method for automatically generating test vectors for digital integrated circuits
JPH0772223A (ja) 1993-07-01 1995-03-17 Matsushita Electric Ind Co Ltd 検査系列生成方法及び検査系列生成装置
US5675729A (en) 1993-10-22 1997-10-07 Sun Microsystems, Inc. Method and apparatus for performing on-chip measurement on a component
US5502647A (en) * 1993-12-01 1996-03-26 Nec Usa, Inc. Resynthesis and retiming for optimum partial scan testing
JPH07191102A (ja) 1993-12-27 1995-07-28 Matsushita Electric Ind Co Ltd 検査系列自動生成装置
JP2737637B2 (ja) 1994-03-02 1998-04-08 日本電気株式会社 論理回路検査装置
JPH07325131A (ja) 1994-06-02 1995-12-12 Matsushita Electric Ind Co Ltd 検査系列圧縮装置
JPH0815388A (ja) * 1994-06-27 1996-01-19 Matsushita Electric Ind Co Ltd 検査系列生成方法及び検査系列生成装置
US5623502A (en) * 1994-07-15 1997-04-22 National Semiconductor Corporation Testing of electronic circuits which typically contain asynchronous digital circuitry
US5668481A (en) 1995-02-23 1997-09-16 National Science Council Multiple pattern sequence generation based on inverting non-linear autonomous machine
US5726996A (en) 1995-09-18 1998-03-10 Nec Usa, Inc. Process for dynamic composition and test cycles reduction

Also Published As

Publication number Publication date
US6651206B2 (en) 2003-11-18
US6253343B1 (en) 2001-06-26
EP1306684B1 (de) 2005-03-30
TW413757B (en) 2000-12-01
EP0874315A1 (de) 1998-10-28
EP1306684A3 (de) 2004-01-21
DE69829593T2 (de) 2005-09-01
US20020026611A1 (en) 2002-02-28
EP0874315B1 (de) 2004-03-31
DE69822694T2 (de) 2004-08-12
DE69822694D1 (de) 2004-05-06
EP1306684A2 (de) 2003-05-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee